Arithmetic apparatus and multiply-accumulate system

ABSTRACT

An arithmetic apparatus includes input lines and one or more multiply-accumulate devices. An electrical signal corresponding to an input value is input into the input lines within a predetermined input period. Multiplication units generate a product value by multiplying the input value by a weight value. An accumulation unit accumulates the charge corresponding to the generated product value. A charging unit charges, after the input period, the accumulation unit in which the charge corresponding to the product value is accumulated. An output unit outputs, after charging by the charging unit starts, a multiply-accumulate signal representing a sum of the product values by performing threshold determination on a voltage retained by the accumulation unit by using a predetermined threshold value. The charging by the charging unit is performed on a common charging mode and a common threshold value is set as the predetermined threshold value.

TECHNICAL FIELD

The present technology relates to an arithmetic apparatus and amultiply-accumulate system that can be applied to a multiply-accumulateoperation using an analog method.

BACKGROUND ART

Conventionally, a technology for performing a multiply-accumulateoperation has been developed. The multiply-accumulate operation is anoperation of multiplying each of a plurality of input values by a weightand adding the multiplication results to each other, and is used for,for example, processing of recognizing images, voices, and the likethrough a neural network or the like.

For example, Patent Literature 1 describes an analog circuit in whichmultiply-accumulate processing is performed in an analog manner. In thisanalog circuit, a weight corresponding to each of a plurality ofelectrical signals is set. Moreover, charges depending on thecorresponding electrical signals and weights are respectively output andthe output charges are accumulated in a capacitor as appropriate. Avalue to be calculated, which represents a multiply-accumulate result,is calculated on the basis of the voltage of the capacitor in which thecharges are accumulated. Accordingly, it is possible to reduce the powerconsumption required for the multiply-accumulate operation as comparedwith, for example, digital processing (paragraphs [0003], [0049] to[0053], and of specification, FIG. 3, and the like of Patent Literature1).

CITATION LIST Patent Literature

Patent Literature 1: WO 2018/034163

DISCLOSURE OF INVENTION Technical Problem

The use of such an analog-type circuit is expected to lead to low powerconsumption of the neural network or the like, and it is desirable toprovide a technology of realizing efficient and high-speed arithmeticprocessing.

In view of the above-mentioned circumstances, it is an object of thepresent technology to provide an arithmetic apparatus, amultiply-accumulate system, and a setting method by which efficient andhigh-speed arithmetic processing can be realized in an analog circuitthat performs a multiply-accumulate operation.

Solution to Problem

In order to accomplish the above-mentioned object, an arithmeticapparatus according to an embodiment of the present technology includesa plurality of input lines and one or more multiply-accumulate devices.

Each of which an electrical signal corresponding to an input value isinput within a predetermined input period into the plurality of inputlines.

The one or more multiply-accumulate devices each include a plurality ofmultiplication units, an accumulation unit, a charging unit, and anoutput unit.

The plurality of multiplication units generates, on the basis of theelectrical signal input into each of the plurality of input lines, acharge corresponding to a product value obtained by multiplying theinput value by a weight value.

The accumulation unit accumulates the charge corresponding to theproduct value generated by each of the plurality of multiplicationunits.

The charging unit charges, after the input period, the accumulation unitin which the charge corresponding to the product value is accumulated.

The output unit outputs, after charging by the charging unit starts, amultiply-accumulate signal representing a sum of the product values byperforming threshold determination on a voltage retained by theaccumulation unit by using a predetermined threshold value.

Moreover, in the one or more multiply-accumulate devices, the chargingby the charging unit is performed on a common charging mode and a commonthreshold value is set as the predetermined threshold value.

In this arithmetic apparatus, with respect to the one or moremultiply-accumulate devices, the charging is performed on the commoncharging mode and the threshold determination is performed by using thecommon threshold value. Accordingly, it is possible to realize efficientand high-speed arithmetic processing in the analog circuit that performsthe multiply-accumulate operation.

The one or more multiply-accumulate devices may be a plurality ofmultiply-accumulate devices connected in parallel to the plurality ofinput lines.

The common charging mode may include charging in which a same chargesignal is supplied during a common charging period.

The common charging mode may include charging at a common chargingspeed.

The common charging mode may include charging according to a common timeconstant.

Defining a sum total of absolute values of the weight values set in theplurality of multiplication units as a weight sum total value, thecommon charging mode may include charging based on a maximum value ofthe weight sum total value among the one or more multiply-accumulatedevices.

Each of the one or more multiply-accumulate devices may include a chargeoutput line. In this case, the plurality of multiplication units mayoutput the charge corresponding to the product value to the chargeoutput line. Moreover, the common charging mode may include charging inwhich a time constant associated with the output of the chargecorresponding to the product value to the charge output line by theplurality of multiplication units the weight sum total value of which isthe maximum value is used as the common time constant.

The common threshold value may be set on the basis of a duration of theinput period.

Defining a sum total of absolute values of the weight values set in theplurality of multiplication units as a weight sum total value, thecommon threshold value may be set on the basis of a maximum value of theweight sum total value among the one or more multiply-accumulatedevices.

The common charging mode may include charging in which a same chargesignal is supplied during the common charging period. In this case, thecharging unit may include a charging line that is connected to theaccumulation unit and supplies the same charge signal to theaccumulation unit during the common charging period.

The common charging mode may include charging in which a same chargesignal is supplied during the common charging period. In this case, thecharging unit may supply the same charge signal to the accumulation unitvia the plurality of input lines during the common charging period.

The plurality of multiplication units may include at least one of apositive weight multiplication unit that generates a positive weightcharge corresponding to a product value obtained by multiplying theinput value by a positive weight value or a negative weightmultiplication unit that generates a negative weight chargecorresponding to a product value obtained by multiplying the input valueby a negative weight value. In this case, the accumulation unit mayinclude a positive charge accumulation unit capable of accumulating thepositive weight charge generated by the positive weight multiplicationunit and a negative charge accumulation unit capable of accumulating thenegative weight charge generated by the negative weight multiplicationunit. Moreover, the charging unit may charge the positive chargeaccumulation unit and the negative charge accumulation unit on thecommon charging mode. Moreover, the output unit may output themultiply-accumulate signal by performing threshold determination on eachof the positive charge accumulation unit and the negative chargeaccumulation unit by using the common threshold value.

Defining a sum total of the positive weight values set in the pluralityof multiplication units as a positive sum total value and a sum total ofthe absolute values of the negative weight values as a negative sumtotal value, the common charging mode may include charging based on amaximum value among the positive sum total values and the negative sumtotal values in the one or more multiply-accumulate devices.

Each of the one or more multiply-accumulate devices may include apositive charge output line and a negative charge output line. In thiscase, the positive charge multiplication unit may output the positiveweight charge to the positive charge output line.

Moreover, the negative charge multiplication unit may output thenegative weight charge to the negative charge output line. Moreover,assuming that the maximum value among the positive sum total values andthe negative sum total values in the one or more multiply-accumulatedevices is a maximum sum total value, that the positive weight charge orthe negative weight charge related to the maximum sum total value is amaximum weight charge, and that the positive charge output line or thenegative charge output line from which the maximum weight charge isoutput is a maximum charge output line, defining a time constantassociated with the output of the maximum weight charge to the maximumcharge output line as a common time constant, the common charging modemay include charging according to the common time constant.

Defining a sum total of the positive weight values set in the pluralityof multiplication units as a positive sum total value and a sum total ofthe absolute values of the negative weight values as a negative sumtotal value, the common threshold value may be set on the basis of amaximum value among the positive sum total values and the negative sumtotal values in the one or more multiply-accumulate devices.

The positive weight value and the absolute value of the negative weightvalue may be fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set. In this case, in theone or more multiply-accumulate devices, a value obtained by adding thepositive sum total value and the negative sum total value may be acommon value.

The positive weight value and the absolute value of the negative weightvalue may be fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set. In this case, in theone or more multiply-accumulate devices, a value obtained by adding thepositive sum total value and the negative sum total value may be arandom value.

The common charging mode may include charging in which a same chargesignal is supplied during the common charging period. In this case, thecharging unit may include a charging line that is connected to thepositive charge accumulation unit and the negative charge accumulationunit and supplies the same charge signal to the positive chargeaccumulation unit and the negative charge accumulation unit during thecommon charging period.

The common charging mode may include charging in which a same chargesignal is supplied during the common charging period. In this case, thecharging unit may supply the same charge signal to the positive chargeaccumulation unit and the negative charge accumulation unit via theplurality of input lines during the common charging period.

A multiply-accumulate system according to an embodiment of the presenttechnology includes a plurality of input lines, one or more analogcircuits, and a network circuit.

The one or more analog circuits includes a plurality of multiplicationunits, an accumulation unit, a charging unit, and an output unit.

The network circuit is configured by connecting the plurality of analogcircuits.

Moreover, in the one or more analog circuits, the charging by thecharging unit is performed on a common charging mode and a commonthreshold value is set as the predetermined threshold value.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 A schematic diagram showing a configuration example of anarithmetic apparatus according to an embodiment of the presenttechnology.

FIG. 2A schematic diagram showing an example of an electrical signal tobe input into an analog circuit.

FIG. 3A schematic diagram showing a specific configuration example of anarithmetic apparatus.

FIG. 4A schematic diagram showing a configuration example of a neuroncircuit.

FIG. 5A schematic circuit diagram showing an example of an analogcircuit of a PWM method.

FIG. 6A diagram for describing a calculation example of amultiply-accumulate signal by the analog circuit shown in FIG. 5.

FIG. 7A schematic diagram showing a calculation example of amultiply-accumulate signal showing the entire multiply-accumulateresult.

FIG. 8 A schematic circuit diagram showing an example of an analogcircuit according to a TACT method.

FIG. 9 A schematic graph for describing a potential of each output lineat the end of the input period.

FIG. 10 A diagram showing a configuration example of an arithmeticapparatus including a plurality of analog circuits according to the PWMmethod.

FIG. 11 A diagram showing a configuration example of an arithmeticapparatus including a plurality of analog circuits according to the PWMmethod.

FIG. 12 A diagram showing a configuration example of an arithmeticapparatus including a plurality of analog circuits according to the TACTmethod.

FIG. 13 A diagram showing a configuration example of an arithmeticapparatus including a plurality of analog circuits according to the TACTmethod.

FIG. 14 A schematic view showing a configuration example of a neuralnetwork.

FIG. 15 A schematic circuit diagram showing another example of theanalog circuit according to the PWM method.

FIG. 16 A schematic circuit diagram showing another example of theanalog circuit according to the PWM method.

FIG. 17 A diagram for describing a calculation example of amultiply-accumulate signal according to the analog circuit shown in FIG.16.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments according to the present technology will bedescribed with reference to the drawings.

[Configuration of Arithmetic Apparatus]

FIG. 1 is a schematic diagram showing a configuration example of anarithmetic apparatus according an embodiment of the present technology.An arithmetic apparatus 100 is an analog-type arithmetic apparatus thatperforms predetermined arithmetic processing including amultiply-accumulate operation. By using the arithmetic apparatus 100,for example, it is possible to perform arithmetic processing accordingto a mathematical model such as a neural network.

The arithmetic apparatus 100 includes a plurality of signal lines 1, aplurality of input units 2, and a plurality of analog circuits 3. Eachof the signal lines 1 is a line that transmits a predetermined type ofelectrical signal. For example, an analog signal representing a signalvalue by using an analog amount such as a pulse timing and a pulse widthis used as the electrical signal. The directions in which electricalsignals are transmitted are schematically shown in FIG. 1 by means ofarrows. In this embodiment, the analog circuits 3 corresponds tomultiply-accumulate devices.

For example, the plurality of signal lines 1 is connected to one analogcircuit 3. The signal line 1 that transmits an electrical signal to theanalog circuit 3 is an input signal line, into which an electricalsignal is input, for the analog circuit 3 to which that signal line 1 isconnected. Moreover, the signal line 1 that transmits an electricalsignal output from the analog circuit 3 is an output signal line, fromwhich an electrical signal is output, for the analog circuit 3 to whichthat signal line 1 is connected. In this embodiment, the input signalline corresponds to an input line.

The plurality of input units 2 each generates a plurality of electricalsignals corresponding to input data 4. The input data 4 is, for example,data to be processed using a neural network or the like implemented bythe arithmetic apparatus 100. Therefore, it can also be said that therespective signal values of the plurality of electrical signalscorresponding to the input data 4 are input values to the arithmeticapparatus 100.

For example, arbitrary data such as image data, audio data, andstatistical data to be processed by the arithmetic apparatus 100 is usedas the input data 4. For example, in a case where image data is used asthe input data 4, an electrical signal using a pixel value (RGB value,luminance value, etc.) of each of pixels of the image data as a signalvalue is generated. In addition, an electrical signal corresponding tothe input data 4 may be generated as appropriate in accordance with thetype of the input data 4 and the contents of the processing performed bythe arithmetic apparatus 100.

The analog circuit 3 is an analog-type circuit that performs amultiply-accumulate operation on the basis of an input electricalsignal. The multiply-accumulate operation is, for example, an operationof adding up a plurality of product values obtained by multiplying aplurality of input values by weight values corresponding to inputvalues. Therefore, it can also be said that the multiply-accumulateoperation is processing of calculating a sum of the product values(hereinafter, referred to as a multiply-accumulate result).

As shown in FIG. 1, a plurality of input signal lines is connected toone analog circuit 3 and a plurality of electrical signals is providedthereto. The plurality of input signal lines and the analog circuitconstitute a multiply-accumulate operation circuit according to thisembodiment. Moreover, a plurality of electrical signals is input fromeach of the input signal lines, and a multiply-accumulate methodaccording to this embodiment is accordingly performed by themultiply-accumulate operation circuit (analog circuit 3).

Hereinafter, it is assumed that the total number of electrical signalsinput into one analog circuit 3 is N. It should be noted that the numberN of electrical signals to be input into each analog circuit 3 is set asappropriate for each circuit in accordance with, for example, the model,accuracy, and the like of arithmetic processing.

In the analog circuit 3, for example, a w_(i)*x_(i) is calculated whichis a product value of a signal value x_(i) represented by an electricalsignal input from an i-th input signal line and a weight value w_(i)corresponding to the signal value x_(i). Here, i represents a naturalnumber equal to or smaller than N (i=1, 2, . . . N). The operation ofthe product value is performed for each electrical signal (input signalline) and N product values are calculated. A value obtained by adding upthe N product values is calculated as a multiply-accumulate result (sumof N product values). Therefore, the multiply-accumulate resultcalculated by one analog circuit 3 is expressed by the followingexpression.

$\begin{matrix}{\sum\limits_{i = 1}^{N}{w_{i} \cdot x_{i}}} & \left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack\end{matrix}$

The weight value w_(i) is set, for example, in the range of −α≤w_(i)≤+α.Here, α represents an arbitrary real value. Thus, the weight value w_(i)may include a positive weight value w_(i), a negative weight valuew_(i), a zero weight value w_(i), and the like. As described above, bysetting the weight value w_(i) to be in a predetermined range, it ispossible to avoid the situation where the multiply-accumulate resultdiverges.

Moreover, for example, the range in which the weight value w_(i) is setmay be normalized. In this case, the weight value w_(i) is set to be ina range of −1≤w_(i)≤1. Accordingly, for example, the maximum value, theminimum value, and the like of the multiply-accumulate result can beadjusted, and the multiply-accumulate operation can be performed with adesired accuracy.

In a neural network or the like, a method called binary connect, whichsets the weight value w_(i) to be either +α or −α, can be used. Thebinary connect is used in various fields such as image recognition usinga deep neural network (multi-layer neural network). The use of thebinary connect can simplify the setting of the weight value w_(i)without deteriorating the recognition accuracy and the like. In thebinary connect, the positive weight value and the absolute value of thenegative weight value are fixed to the same value.

As described above, in the binary connect, the weight value w_(i) isbinarized into a binary value (±α). Thus, a desired weight value w_(i)can be easily set by changing the weight value w_(i) to be positive ornegative, for example. Alternatively, the binarized weight value w_(i)may be normalized and the weight value w_(i) may be set to ±1.

Moreover, the weight value wi may be multivalued. In this case, theweight value wi is set by selecting from a plurality of discrete weightvalue candidates. Examples of the weight value candidates include (−3,−2, −1, 0, 1, 2, 3) and (1, 2, 5, 10). Moreover, standardized weightvalue candidates (−1, −0.5, 0, 0.5, 1) or the like may be used. A valueis selected from among these weight value candidates and is set as theweight value wi. The number of weight value candidates, the method ofsetting the candidate values, and the like are not limited. Bymultivaluing the weight value wi, it is possible to construct a neuralnetwork or the like with high versatility, for example.

In addition, the setting range, the setting value, and the like of theweight value w_(i) are not limited, and may be set as appropriate suchthat desired processing accuracy is realized, for example. For example,the weight value w_(i) may be randomly set.

The signal values x_(i) are, for example, electrical signals output fromthe input units 2 and multiply-accumulate results output from the analogcircuits 3. In this way, it can also be said that the input units 2 andthe analog circuits 3 function as signal sources for outputting thesignal values x_(i).

In the example shown in FIG. 1, a single electrical signal (singlesignal value x_(i)) is output from one signal source (input unit 2,analog circuit 3). Therefore, the same electrical signal is input intoeach of the plurality of signal lines 1 connected to an output side ofthe one signal source. Moreover, one signal source and the analogcircuit 3 into which the electrical signal output from the signal sourceis input are connected to each other by a single input signal line.

Therefore, for example, M input signal lines are connected to the analogcircuit 3 connected to M signal sources in the arithmetic apparatus 100shown in FIG. 1. In this case, the total number N of electrical signalsinput into the analog circuits 3 is N=M. It should be noted that aconfiguration in which a pair of electrical signals corresponding topositive and negative values (pair of signal values x_(i) ⁺, x_(i) ⁻) isoutput from one signal source is possible.

As shown in FIG. 1, the arithmetic apparatus 100 has a layered structurein which the plurality of analog circuits 3 is provided in each of aplurality of layers. By configuring the layer structure of the analogcircuits 3, a multi-layer perceptron-type neural network or the like,for example, is constructed. The number of analog circuits provided ineach layer, the number of layers, and the like are designed asappropriate such that desired processing can be performed, for example.Hereinafter, the number of analog circuits 3 provided in a j-th layerwill be sometimes referred to as N_(j).

For example, N electrical signals generated by N input units 2 are inputinto each analog circuit 3 provided in a layer of a first stage (lowestlayer). The analog circuits 3 of the first stage calculatemultiply-accumulate results related to the signal values x_(i) of theinput data, and output the calculated multiply-accumulate results to theanalog circuits 3 provided in a next layer (second stage) after thenon-linear conversion processing.

N₁ electrical signals representing the respective multiply-accumulateresults calculated in the first stage are input into the respectiveanalog circuits 3 provided in a second layer (upper layer). Therefore,as viewed from the analog circuits 3 of the second stage, the non-linearconversion processing results of the respective multiply-accumulateresults calculated in the first stage are the signal values x_(i) of theelectrical signals. The analog circuits 3 of the second stage calculatethe multiply-accumulate results of the signal values x_(i) output fromthe first stage, and output the calculated multiply-accumulate resultsto the analog circuits 3 of the upper layer.

In this way, in the arithmetic apparatus 100, the multiply-accumulateresults of the analog circuits 3 in the upper layer are calculated onthe basis of the multiply-accumulate results calculated by the analogcircuits 3 in the lower layer. Such processing is performed multipletimes, and the processing results are output from the analog circuits 3included in the top layer (the layer of the third stage in FIG. 1).Accordingly, for example, processing such as image recognition ofdetermining that the object is a cat on the basis of image data (inputdata 4) obtained by imaging the cat can be performed.

As described above, a desired network circuit can be configured byconnecting the plurality of analog circuits 3 as appropriate. Thenetwork circuit functions as a data flow processing system that performsarithmetic processing by, for example, causing signals to passtherethrough. In the network circuit, various processing functions canbe realized by setting, for example, a weight value (synapse connection)as appropriate. With this network circuit, the multiply-accumulatesystem according to this embodiment is constructed.

It should be noted that the method of connecting the analog circuits 3to each other and the like are not limited, and, for example, theplurality of analog circuits 3 may be connected to each other asappropriate such that desired processing can be performed. For example,the present technology can be applied even in a case where the analogcircuits 3 are connected to each other so as to configure anotherstructure different from the layered structure.

In the above description, the configuration in which themultiply-accumulate results calculated in the lower layer are input intothe upper layer as they are has been described. The present technologyis not limited thereto, and, for example, conversion processing or thelike may be performed on the multiply-accumulate results. For example,in the neural network model, processing of, for example, performingnon-linear conversion on the multiply-accumulate result of each analogcircuit 3 by using an activation function and inputting the conversionresults to the upper layer is performed.

In the arithmetic apparatus 100, a function circuit 5 or the like thatperforms non-linear conversion using an activation function on theelectrical signal, for example, is used. The function circuit 5 is, forexample, a circuit that is provided between a lower layer and an upperlayer and that converts a signal value of an input electrical signal asappropriate and outputs an electrical signal according to the conversionresult. The function circuit 5 is provided for each of the signal lines1, for example. The number of function circuits 5, the arrangement ofthe function circuits 5, and the like are set as appropriate inaccordance with, for example, the mathematical model implemented in thearithmetic apparatus 100.

For example, a ReLU function (ramp function) or the like is used as theactivation function. The ReLU function outputs the signal value x_(i) asit is in a case where the signal value x_(i) is 0 or more, for example,and outputs 0 otherwise. For example, the function circuit 5 thatimplements the ReLU function is connected to each of the signal lines 1as appropriate. Accordingly, it is possible to realize the processing ofthe arithmetic apparatus 100.

FIG. 2 is a schematic diagram showing an example of the electricalsignal input into the analog circuit 3. In each of FIGS. 2A and B, agraph representing a waveform of a plurality of electrical signals isschematically shown. The horizontal axis of the graph indicates the timeaxis and the vertical axis indicates the voltage of the electricalsignal.

An exemplary waveform of an electrical signal according to a pulse widthmodulation (PWM) method is shown in FIG. 2A. The PWM method is a methodof representing a signal value x_(i) by using a pulse width τ_(i) of apulse waveform, for example. That is, in the PWM method, the pulse widthτ_(i) of the electrical signal is a length depending on the signal valuex_(i).

Typically, the longer the pulse width τ_(i), the higher the signal valuex_(i).

Moreover, the electrical signal is input into the analog circuit 3within a predetermined input period T. More specifically, the respectiveelectrical signals are input into the analog circuits 3 such that thepulse waveforms of the electrical signals fall in the input period T.Therefore, the maximum value of the pulse width of the electrical signalis similar to the input period T. It should be noted that the timing atwhich each pulse waveform (electrical signal) are input and the like arenot limited as long as the pulse waveform falls in the input period T.

In the PWM method, for example, a duty ratio R_(i) (=T_(i)/T) of thepulse width τ_(i) to the input period T can be used to normalize thesignal value x_(i). That is, the normalized signal value x_(i) isrepresented as the signal value x_(i)=R_(i). It should be noted that themethod of associating the signal value x_(i) with the pulse width τ_(i)is not limited and, for example, the pulse width τ_(i) representing thesignal value x_(i) may be set as appropriate such that the calculationprocessing or the like can be performed with a desired accuracy.

In a case where the electrical signal according to the PWM method isused, a time-axis analog multiply-accumulate operation using the analogcircuit 3 according to the PWM method can be performed.

In FIG. 2B, an exemplary waveform of the electrical signal of a spiketiming method (hereinafter, referred to as TACT method) is shown. TheTACT method is a method of representing a signal value x_(i) by usingthe rising timing of the pulse, for example. For example, a pulse isinput at a timing corresponding to the input value by using apredetermined timing as a reference.

The electrical signal is input into the analog circuit 3 within thepredetermined input period T. The signal value x_(i) is represented bythe input timing of the pulse within this input period T. For example, alargest signal value x_(i) is represented by a pulse input at the sametime as the start of the input period T. A smallest signal value x_(i)is represented by a pulse input at the same time as the end of the inputperiod T.

It can also be said that the signal value xi is represented by theduration from the input timing of the pulse to the end timing of theinput period T. For example, the largest signal value x_(i) isrepresented by a pulse whose duration from the input timing of the pulseto the end timing of the input period T is equal to the input period T.The smallest signal value x_(i) is represented by a pulse whose durationfrom the input timing of the pulse to the end timing of the input periodT is 0.

It should be noted that in the FIG. 2B, a continuous pulse signal thatrises to a timing corresponding to the input value and keeps the ONlevel until the multiply-accumulate result is obtained is used as theelectrical signal according to the TACT method. The present technologyis not limited thereto, and a rectangular pulse or the like having apredetermined pulse width may be used as the electrical signal accordingto the TACT method.

In a case where the electrical signal according to the TACT method isused, a time-axis analog multiply-accumulate operation using the analogcircuit 3 according to the TACT method can be performed.

As illustrated in FIGS. 2A and B, a pulse signal whose duration of theON time with respect to the input period T corresponds to the inputvalue can be used as the electrical signal corresponding to the inputvalue. It should be noted that hereinafter, the description will be madeassuming that the signal value x_(i) represented by each electricalsignal is a variable of 0 or more and 1 or less.

FIG. 3 is a schematic diagram showing a specific configuration exampleof the arithmetic apparatus 100. FIG. 3 is an arrangement example ofcircuits for realizing the arithmetic apparatus 100 shown in FIG. 1, forexample, and schematically shows the plurality of analog circuits 3provided in one layer of the arithmetic apparatus 100.

The analog circuits 3 each include a pair of output lines 7, a pluralityof synapse circuits 8, and a neuron circuit 9. As shown in FIG. 3, oneanalog circuit 3 is configured to extend in a predetermined direction(vertical direction in the figure). A plurality of such analog circuits3 extending in the vertical direction are arranged side by side in thehorizontal direction, to thereby form one layer.

Hereinafter, it is assumed that the analog circuit 3 disposed on theleftmost side in the figure is a first analog circuit 3. Moreover, thedirection in which the analog circuits 3 extend will be sometimesreferred to as an extension direction.

The pair of output lines 7 is spaced apart from each other along theextension direction. The pair of output lines 7 includes a positivecharge output line 7 a and a negative charge output line 7 b. Each ofthe positive charge output line 7 a and the negative charge output line7 b is connected to the neuron circuit 9 via the plurality of synapsecircuits 8.

The synapse circuit 8 calculates a product value (w_(i)*x_(i)) of thesignal value x_(i) represented by the electrical signal and the weightvalue w_(i).

Specifically, a charge (current) corresponding to the product value isoutput to either the positive charge output line 7 a or the negativecharge output line 7 b.

As will be described later, either the positive weight value w_(i) ⁺ orthe negative weight value is set to the synapse circuit 8. For example,a positive weight charge corresponding to the product value of thepositive weight value w_(i) ⁺ is output to the positive charge outputline 7 a. Moreover, for example, a negative weight charge correspondingto the product value of the negative weight value w_(i) ⁻ is output tothe negative charge output line 7 b.

It should be noted that in the synapse circuit 8, a charge with the samesign (e.g., a positive charge) is output as the charge corresponding tothe product value irrespective of whether the weight value w_(i) ispositive or negative. That is, the positive weight charge and thenegative weight charge become charges with the same sign.

In this way, the synapse circuits 8 are each configured to output thecharge corresponding to the multiplication result to the differentoutput line 7 a or 7 b in accordance with the sign of the weight valuewi. A specific configuration of the synapse circuit 8 will be describedlater in detail. In this embodiment, the plurality of synapse circuits 8functions as a plurality of multiplication units that generates a chargecorresponding to a product value obtained by multiplying an input valueby a weight value on the basis of an electrical signal input into eachof the plurality of input lines.

In this embodiment, the single input signal line 6 and the pair ofoutput lines 7 are connected to the single synapse circuit 8. That is, asingle electrical signal is input into the single synapse circuit 8 anda charge corresponding to the product value calculated on the basis ofthe input electrical signal is output to either the output line 7 a or 7b. Thus, the synapse circuit 8 is a one-input two-output circuitconnected to the single input signal line 6 and the pair of output lines7 (positive charge output line 7 a and the negative charge output line 7b).

In one analog circuit 3, the plurality of synapse circuits 8 is arrangedalong the pair of output lines 7. Each synapse circuits 8 is connectedin parallel to the positive charge output line 7 a (negative chargeoutput line 7 b). Hereinafter, it is assumed that the synapse circuit 8disposed on a most downstream side (side connected to the neuron circuit9) is a first synapse circuit.

As shown in FIG. 3, the plurality of input signal lines 6 is wired so asto intersect with the pair of output lines 7 of each of the plurality ofanalog circuits 3. Typically, the input signal line 6 is provided to beorthogonal to each output line 7. That is, the arithmetic apparatus 100has a crossbar configuration in which the input signal lines 6 and theoutput lines 7 cross each other. With the crossbar configuration, theanalog circuits 3 and the like, for example, can be integrated at highdensity.

Moreover, in the arithmetic apparatus 100, j-th synapse circuits 8included in the respective analog circuits 3 are connected in parallelto a j-th input signal line 6. Therefore, similar electrical signals areinput into the synapse circuits 8 connected to the same input signalline 6. Accordingly, a configuration in which one signal source includedin the lower layer is connected to a plurality of analog circuits 3included in the upper layer can be implemented.

It should be noted that in the example shown in FIG. 3, the analogcircuit 3 (pre-neuron) included in the lower layer is schematicallyshown as a signal source that inputs an electrical signal into each ofthe input signal lines 6. The present technology is not limited thereto,and, for example, the crossbar configuration can be used also in a casewhere the input unit 2 is used as the signal source.

As described above, in the arithmetic apparatus 100, the plurality ofanalog circuits 3 is connected in parallel to each of the plurality ofinput signal lines 6. Accordingly, for example, it is possible to inputan electrical signal in parallel into each analog circuit 3 (eachsynapse circuit 8) and to achieve arithmetic processing at high speed.As a result, it is possible to exhibit excellent operation performance.

The neuron circuit 9 calculates a multiply-accumulate result shown inthe expression (Formula 1) on the basis of the product values calculatedby the synapse circuits 8. Specifically, the neuron circuit 9 outputs anelectrical signal representing the multiply-accumulate result(multiply-accumulate signal) on the basis of charges input via the pairof output lines 7.

FIG. 4 is a schematic diagram showing a configuration example of theneuron circuit 9. The neuron circuit 9 includes an accumulation unit 11and a signal output unit 12. FIG. 4 shows a two-input one-output neuroncircuit 9 connected to a pair of output lines 7 and a single outputsignal line 10. It should be noted that a two-input two-output circuitor the like can be used as the neuron circuit 9 in some cases.

The accumulation unit 11 accumulates charges output to the pair ofoutput lines 7 by the plurality of synapse circuits 8. The accumulationunit 11 includes two capacitors 13 a and 13 b. The capacitor 13 a isconnected between the positive charge output line 7 a and the GND.Moreover, the capacitor 13 b is connected between the negative chargeoutput line 7 b and the GND. Therefore, charges flowing in from thepositive charge output line 7 a and the negative charge output line 7 bare respectively accumulated in the capacitors 13 a and 13 b.

For example, when the input period T of the electrical signal haselapsed, the charges accumulated in the capacitor 13 a are a sum totalσ⁺ of positive weight charges each corresponding to the product value ofthe positive weight value w_(i) ⁺. Also, the charges accumulated in thecapacitor 13 b are a sum total σ⁻ of negative weight chargescorresponding to the product value of the negative weight value w_(i) ⁻.

For example, in a case where the positive weight charges are accumulatedin the capacitor 13 a, the potential of the positive charge output line7 a with reference to the GND increases. Therefore, the potential of thepositive charge output line 7 a is a value depending on the sum total σ⁺of the charges each corresponding to the product value of the positiveweight value w_(i) ⁺+. It should be noted that the potential of thepositive charge output line 7 a corresponds to the voltage retained bythe capacitor 13 a.

Similarly, in a case where the negative weight charges are accumulatedin the capacitor 13 b, the potential of the negative charge output line7 b with reference to the GND increases. Therefore, the potential of thenegative charge output line 7 b is a value depending on the sum total σ⁻of the charges each corresponding to the product value of the negativeweight value w_(i) ⁻. It should be noted that the potential of thenegative charge output line 7 b corresponds to the voltage retained bythe capacitor 13 b.

The signal output unit 12 outputs a multiply-accumulate signalrepresenting a sum of the product values (w_(i) ⁺*x_(i)) on the basis ofthe charges accumulated in the accumulation unit 11. Themultiply-accumulate signal is, for example, a signal representing atotal multiply-accumulate result, which is a sum of product values ofall positive and negative weight values w_(i) and signal values x_(i).For example, the multiply-accumulate result represented by theexpression (Formula 1) can be written as follows.

$\begin{matrix}{{\sum\limits_{i = 1}^{N}{w_{i}x_{i}}} = {{\sum\limits_{i = 1}^{N^{+}}{w_{i}^{+}x_{i}}} - {\sum\limits_{i = 1}^{N^{-}}{{w_{i}^{-}}x_{i}}}}} & \left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack\end{matrix}$

Here, N⁺ and N⁻ are the total number of positive weight values w_(i) ⁺and the total number of negative weight values w_(i) ⁻, respectively. Asshown in the expression (Formula 2), the total multiply-accumulateresult can be calculated as a difference between a multiply-accumulateresult of positive weight charges, which is a sum total of productvalues (w_(i) ⁺*x_(i)) of the positive weight values w_(i) ⁺, and amultiply-accumulate result of negative weight charges, which is a sumtotal of product values (|w_(i) ⁻|*x_(i)) of the negative weight valuesw_(i) ⁻.

In the example shown in FIG. 4, the signal output unit 12 generates onesignal representing the total multiply-accumulate result, for example,as the multiply-accumulate signal. Specifically, by referring to thecharges accumulated in the accumulation unit 11 (capacitors 13 a and 13b) as appropriate, a positive multiply-accumulate result and a negativemultiply-accumulate result are calculated, and the totalmultiply-accumulate result is calculated on the basis of the differencetherebetween. Moreover, for example, two signals of a positivemultiply-accumulate signal and a negative multiply-accumulate signalrespectively representing the positive and negative multiply-accumulateresults may be generated as the multiply-accumulate signals.

The method of referring to the charges accumulated in the accumulationunit 11 is not limited. As an example, a method of detecting chargesaccumulated in one capacitor 13 will be described. In a case where theelectrical signal according to the PWM method illustrated in FIG. 2A isused, the charges each corresponding to the product value areaccumulated in the capacitor 13 within the input period T. That is, theaccumulation of charges each corresponding to the product value does notoccur before and after the input period T.

For example, after the input period T ends, the capacitor 13 is chargedat a predetermined charging speed. At this time, a comparator or thelike is used to detect a timing at which the potential of the outputline to which the capacitor 13 is connected reaches a predeterminedthreshold potential. For example, as more charges are accumulated at thetime of starting charging, the timing at which the potential reaches thethreshold potential becomes earlier. Therefore, the charges(multiply-accumulate result) accumulated within the input period T canbe represented on the basis of the timing. It should be noted that thecharging speed can be expressed by, for example, a charge amount perunit time, and can also be referred to as a charging rate.

It should be noted that this threshold determination corresponds toincreasing the voltage retained by the capacitor 13 by charging anddetecting the timing at which the threshold voltage is reached.

In a case where the electrical signal according to the TACT methodillustrated in FIG. 2B is used, charges are accumulated in the capacitor13 because the ON level is maintained also after the input period Tends. For this charge accumulation, the timing at which the potential ofthe output line to which the capacitor 13 is connected reaches thepredetermined threshold potential is detected by using the comparator orthe like. For example, as more charges are accumulated at the end ofinput period T, the timing at which the potential reaches the thresholdpotential becomes earlier. Therefore, the charges (multiply-accumulateresult) accumulated within the input period T can be represented on thebasis of the timing. 4

It should be noted that this threshold determination corresponds todetecting the timing at which the voltage retained by the capacitor 13reaches the threshold voltage.

For example, by performing such threshold determination, a timing torepresent the multiply-accumulate result is detected. Themultiply-accumulate signal of positive weight charges, themultiply-accumulate signal of negative weight charges, or the totalmultiply-accumulate signal is generated as appropriate on the basis ofthe detection result. In addition, each multiply-accumulate result maybe calculated by directly reading the potential of the capacitor 13 whenthe input period T ends, for example.

It should be noted that the voltage depending on the accumulatedpositive weight charges and the voltage depending on the accumulatednegative weight charges may be each amplified in order to generate themultiply-accumulate signal. Moreover, the multiply-accumulate signal maybe generated by amplifying the differential voltage between the voltagedepending on the accumulated positive weight charges and the voltagedepending on the accumulated negative weight charges. For example, adifferential amplifier or the like having an arbitrary configuration maybe provided in the neuron circuit 9.

In this embodiment, the neuron circuit 9 functions as an output unitthat accumulates charges corresponding to the product values generatedby the plurality of multiplication units and outputs amultiply-accumulate signal representing a sum of the product values onthe basis of the accumulated charges.

Moreover, the capacitor 13 a and the capacitor 13 b functions as apositive charge accumulation unit and a negative charge accumulationunit. The neuron circuit 9 accumulates at least one of a positive weightcharge generated by a positive weight multiplication unit and a negativeweight charge generated by a negative weight multiplication unit, tothereby output a multiply-accumulate signal.

Moreover, as it will be described in detail later, in this embodiment,the charging unit is configured, and the accumulation unit 11 (capacitor13) in which the charge corresponding to the product value isaccumulated is charged after the input period T. It should be noted thatthe charging according to the present technology includes accumulatingthe charge in the capacitor 13 by the pulse signal whose ON level iskept in a case where the electrical signal according to the TACT methodis used.

The signal output unit 12 functions as an output unit for outputting amultiply-accumulate signal representing the sum of the product values byperforming threshold determination using a predetermined threshold valueon the voltage retained by the accumulation unit 11 after the chargingunit starts charging. The signal output unit 12 outputs themultiply-accumulate signal by performing the threshold determination foreach of the positive charge accumulation unit and the negative chargeaccumulation unit.

[Analog Circuit According to PWM Method]

FIG. 5 is a schematic circuit diagram showing an example of the analogcircuit according to this embodiment. In FIG. 5, an example of theanalog circuit 3 according to the PWM method is shown. The analogcircuit 3 is provided extending in a direction orthogonal to theplurality of input signal lines 6. That is, in the example shown in FIG.5, the crossbar configuration is employed.

The analog circuit 3 includes the pair of output lines (positive chargeoutput line 7 a and negative charge output line 7 b), a plurality ofsynapse circuits (plurality of multiplication units) 8, a neuron circuit9, and a charging unit 15. In the example shown in FIG. 5, the neuroncircuit 9 includes the accumulation unit 11, a signal output unit 12,and switches 16 a and 16 b.

Pulse signals (PWM signals) each having a pulse width corresponding tothe signal value x_(i) are input into the plurality of input signallines 6 as input signals in₁ to in₆. In the example shown in FIG. 5, sixinput signal lines 6 are shown, though the number of input signal lines6 is not limited. The input signals in₁ to in₆ are input within theinput period T having a predetermined duration (see FIG. 6).

The positive charge output line 7 a outputs the positive weight chargescorresponding to the product values (w_(i)+*x_(i)) each obtained bymultiplying the signal value x_(i) by the positive weight value w_(i) ⁺.The negative charge output line 7 b outputs the negative weight chargescorresponding to the product values (|w_(i) ⁻|*x_(i)) each obtained bymultiplying the signal value x_(i) by the negative weight value w_(i) ⁻.In this embodiment, the pair of output lines 7 corresponds to one ormore output lines.

The plurality of synapse circuits 8 is provided to be associated withthe plurality of input signal lines 6, respectively. In this embodiment,one synapse circuit 8 is provided in one input signal line 6. Each ofthe plurality of synapse circuits 8 includes a resistor 17 that isconnected between the corresponding input signal line 6 of the pluralityof input signal lines 6 and any one of the positive charge output line 7a or the negative charge output line 7 b. This resistor 17 may have anon-linear characteristic and may have a function of preventing backflowof current. A charge corresponding to the product value (w_(i)+*x_(i))(or (|w_(i) ⁻|*x_(i))) is output to the output line 7 a (or 7 b) towhich the resistor 17 is connected.

For example, in order to multiply the signal value x_(i) by the positiveweight value w_(i) ⁺ in each synapse circuit 8, the resistor 17 isconnected between the input signal line 6 and the positive charge outputline 7 a and the positive charge output line 7 a is made to output apositive weight charge. In the example shown in FIG. 5, the synapsecircuit 8 into which the input signal in₁, in₃, in₆ is input is asynapse circuit 8 a configured as the positive weight multiplicationunit that generates a positive weight charge. It can also be said thatthe synapse circuit 8 a is a multiplication unit in which a positiveweight is set.

In order to multiply the signal value x_(i) by the negative weight valuein each synapse circuit 8, the resistor 17 is connected between theinput signal line 6 and the negative charge output line 7 b and thenegative charge output line 7 b is made to output a negative weightcharge. In the example shown in FIG. 5, the synapse circuit 8 into whichthe input signal in₂, in₄, in₅ is input is a synapse circuit 8 bconfigured as the negative weight multiplication unit that generates anegative weight charge. It can also be said that the synapse circuit 8 bis a multiplication unit in which a negative weight is set.

Hereinafter, the synapse circuits 8 a and 8 b will be sometimes referredto as a positive weight multiplication unit 8 a and a negative weightmultiplication unit 8 b. Moreover, the resistor 17 connected between theinput signal line 6 and the positive charge output line 7 a will besometimes referred to as a positive resistor 17 a. Moreover, theresistor 17 connected between the input signal line 6 and the negativecharge output line 7 b will be sometimes referred to as a negativeresistor 17 b.

It should be noted that a resistor having a resistance valuecorresponding to the weight value w_(i) to be set is used as theresistor 17. That is, the resistor 17 functions as an element thatdefines the weight value w_(i) in the arithmetic apparatus 100 thatperforms multiply-accumulate operations at the analog circuits 3.

For example, a fixed resistor element, a variable resistor element, aMOS transistor that operates in a sub-threshold region, or the like isused as the resistor 17. By using a MOS transistor that operates in thesub-threshold region as the resistor 17, for example, it is possible toreduce the power consumption. As a matter of course, another arbitraryresistor may be used.

The accumulation unit 11 accumulates charges corresponding to theproduct values (w_(i)*x_(i)) generated by the plurality of synapsecircuits 8. In this embodiment, two capacitors 13 a and 13 b areprovided as the accumulation unit 11.

The capacitor 13 a is connected to the positive charge output line 7 avia the switch 16 a to accumulate the positive weight charges generatedby the synapse circuits 8 a. The capacitor 13 b is connected to thenegative charge output line 7 b via the switch 16 b to accumulate thenegative weight charges generated by the synapse circuits 8 b.

The charging unit 15 charges the accumulation unit 11 in which a sum ofcharges corresponding to the product values (w_(i)*x_(i)) isaccumulated. In this embodiment, the charging unit 15 includes a signalsource (not shown), a charging line 19, and two resistors 20.

The charging line 19 is arranged in parallel with the input signal line6. A resistor 20 a of the two resistors 20 is connected between thecharging line 19 and the positive charge output line 7 a. Anotherresistor 20 b is connected between the charging line 19 and the negativecharge output line 7 b. Therefore, the charging line 19 is connected tothe capacitor 13 a via the resistor 20 a. Moreover, the charging line 19is connected to the capacitor 13 a via the resistor 20 b.

The resistors 20 a and 20 b having the same resistance value are used.Although the same resistors are typically used, different types ofresistors having the same resistance value may be used. The specificconfigurations of the resistors 20 a and 20 b are not limited, variousconfigurations may be used as in the resistor 17. Moreover, the sameresistors as the resistor 17 or resistors different from the resistor 17may be used as the resistors 20 a and 20 b.

The charging is performed after the input period T ends. In thisembodiment, a charge signal CH is input via the charging line 19 afterthe input period T ends. That is, the same charge signal CH is suppliedto the capacitors 13 a and 13 b from the charging line 19. Thus, chargesbased on the high-level value of the charge signal CH and the resistancevalues of the resistors 20 a and 20 b are accumulated in the capacitors13 a and 13 b.

Since the resistance values of the resistors 20 a and 20 b are valuesequal to each other, the capacitors 13 a and 13 b are charged at thesame charging speed. By the charging by the charging unit 15, thepotential V⁺ of the positive charge output line 7 a (the voltageretained by the capacitor 13 a) and the potential V⁻ of the negativecharge output line 7 b (the voltage retained by the capacitor 13 b) areeach increased.

After the charging unit 15 starts charging, the signal output unit 12performs threshold determination on the voltage retained by theaccumulation unit 11 on the basis of a predetermined threshold value, tothereby output a multiply-accumulate signal representing a sum of theproduct values (w_(i)*x_(i)). In this embodiment, two comparators 22 aand 22 b and a signal generation unit 23 are provided as the signaloutput unit 12.

The comparator 22 a detects a timing at which the voltage retained bythe capacitor 13 a exceeds a predetermined threshold value. It should benoted that the magnitude of the voltage retained by the capacitor 13 ais determined by the total amount of positive weight charge accumulatedin the capacitor 13 a and the charge amount (charging speed x time).

The comparator 22 b detects a timing at which the voltage retained bythe capacitor 13 b exceeds a predetermined threshold value. It should benoted that the magnitude of the voltage retained by the capacitor 13 bis determined by the total amount of negative weight charge accumulatedin the capacitor 13 b and the charge amount (charging speed x time).

It should be noted that in this embodiment, a multiply-accumulate signalis output by performing threshold determination on each of thecapacitors 13 a and 13 b with a common threshold value θ. Accordingly,it is possible to improve the efficiency and speed of the operation. Asa matter of course, also in a case where threshold values different fromeach other are used, the multiply-accumulate operation is possible.

The signal generation unit 23 outputs a multiply-accumulate signalrepresenting a sum of the product values (w_(i)*x_(i)) on the basis ofthe timing detected by the comparator 22 a and the timing detected bythe comparator 22 b. In other words, the signal generation unit 23outputs a multiply-accumulate signal on the basis of a timing at whichthe voltage retained by the capacitor 13 a reaches the threshold value θand a timing at which the voltage retained by the capacitor 13 b reachesthe threshold value θ.

In this embodiment, a PMW signal, which is a pulse signal the pulsewidth of which has been modulated, is output as the multiply-accumulatesignal. The specific circuit configuration and the like of the signalgeneration unit 23 are not limited and may be arbitrarily designed.

FIGS. 6 and 7 are diagrams for describing a calculation example of themultiply-accumulate signal by the analog circuit 3 shown in FIG. 5. Inthis embodiment, a signal representing the total multiply-accumulateresult including the positive and negative values is calculated on thebasis of the multiply-accumulate result of positive weight charges basedon the positive weight charges accumulated in the capacitor 13 a and themultiply-accumulate result of negative weight charges based on thenegative weight charges accumulated in the capacitor 13 b.

The calculation of the multiply-accumulate result of the positive weightcharges and the calculation of the multiply-accumulate result of thenegative weight charges are the same processing. First, a method(multiply-accumulate method) of calculating the multiply-accumulateresult on the basis of the charges accumulated in the capacitor 13without discrimination between positive and negative values will bedescribed with reference to FIG. 6.

The parameters described in FIG. 6 will be described. “t” representstime. “T” represents each of the input period and the output period.“t_(n)” represents an end timing of the input period T and “t_(m)”represents an end timing of the output period T.

In this embodiment, the duration of the input period T and the durationof the output period T are set to be equal to each other. Moreover, theoutput period T is started from an end timing t_(n) of the input periodT. Therefore, the end timing t_(n) of the input period T corresponds tothe start timing of the output period T.

Moreover, in this embodiment, the charging unit 15 performs charging inthe output period T after the input period T. Thus, the output period Tcorresponds to the charging period.

“θ” represents a common threshold value used for threshold determinationperformed by the signal output unit 12 (comparator 22 ).

“S_(i)(t)” represents an input signal (PWM signal) input into an i-thinput signal line 6. “τ_(i)” represents the pulse width of the inputsignal S_(i)(t). “P_(i)(t)” represents an amount of change of aninternal state (potential) in each synapse circuit 8 shown in FIG. 5.“w_(i)” represents a weight value and is defined by the resistance valueof the resistor 17 shown in FIG. 5.

“V_(n)(t)” represents a sum total of “P_(i)(t)” and corresponds to thetotal amount of charge accumulated in the capacitor 13. “S_(n)(t)”represents a multiply-accumulate signal (PWM signal) representing themultiply-accumulate result. “τ_(n)” represents the pulse width of themultiply-accumulate signal to be output. Specifically, “T_(n)”represents a value corresponding to the duration from the timing atwhich the voltage retained by the capacitor 13 exceeds the thresholdvalue θ in the output period T to the end timing t_(m) of the outputperiod T.

“CH(t)” is a charge signal input into the charging line 19 in the outputperiod T that is the charging period. As shown in FIG. 6, in thisembodiment, the pulse signal that becomes ON level during the outputperiod T is input as the charge signal. Therefore, the pulse widthτ_(CH) of the charge signal is equal to the pulse width of the chargesignal in the output period T.

In this example, the switches 16 a and 16 b are provided, and, inparticular, it is possible to improve the reduction of the powerconsumption by disconnecting the output line through this switch.

Here, as shown in the following expression, the input value (signalvalue) x_(i) is given by the duty ratio R_(i) (=τ/T) of the pulse widthτ_(i) of the input signal S_(i)(t) to the input period T.

$\begin{matrix}{x_{i} = {R_{i}\left( {= \frac{\tau_{i}}{T}} \right)}} & \left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack\end{matrix}$

The synapse circuit 8 shown in FIG. 5 generates the charge correspondingto the product value obtained by multiplying the signal value x_(i) bythe weight value w_(i). Specifically, the resistance of the resistor 17increases the internal state (potential) at a constant slope w_(i).

The amount of change P_(i)(t_(n)) of the internal potential of eachsynapse circuit 8 at the end timing t_(n) of the input period T is givenby the following expression. It should be noted that the high-levelvalue of the input-signal S_(i)(t) is set to 1.

P _(i)(t _(n))=w _(i) R _(i) T=w _(i) x _(i) T   [Formula 4]

The total amount V_(n)(t_(n)) of charge accumulated in the capacitor 13is a sum total of Pi(t_(n)), and thus it is given by the followingexpression.

$\begin{matrix}{{V_{n}\left( t_{n} \right)} = {{\sum\limits_{i = 1}^{N}{P_{i}\left( t_{n} \right)}} = {T{\sum\limits_{i = 1}^{N}{w_{i}x_{i}}}}}} & \left\lbrack {{Formula}\mspace{14mu} 5} \right\rbrack\end{matrix}$

Charging by the charging unit 15 (current source 18) is started at theend timing t_(n) of the input period T. As described above, in thisembodiment, the output period T corresponds to the charging period.

By charging by the charging unit 15, the internal potential of eachsynapse circuit 8 is increased at the slope α from the end timing t_(n)of the input period T. The charging speed α is defined by the high-levelvalue of the charge signal and the resistance value of the resistor 20.It should be noted that the illustration of the change in the internalpotential of each synapse circuit 8 in the output period T is omittedfrom FIG. 6 (the value of the internal potential at the end of the inputperiod T is schematically shown by the broken line).

A pulse signal whose high-level value is equal to that of the inputsignal may be used as the charge signal. As a matter of course, a pulsesignal whose high-level value is different from that of the input signalmay be used. Any other electrical signal different from the input signalcan be employed as the charge signal.

A multiply-accumulate signal (PWM signal) having a pulse width T,corresponding to the duration from the timing at which the voltageretained by the capacitor 13 exceeds the threshold value θ in the outputperiod T to the end timing t_(m) of the output period T is generated.

Assuming that the duty ratio of the pulse width τ_(n) of themultiply-accumulate signal to the output period T is R_(n) (=ι_(n)/T),R_(n) is given by the following expression. It should be noted that thethreshold value θ is equal to or larger than the total amountV_(n)(t_(n)) of charge.

$\begin{matrix}{R_{n} = {\frac{T - \frac{\left( {\theta - {V_{n}\left( t_{n} \right)}} \right)}{\alpha}}{T} = {{\frac{1}{\alpha}{\sum\limits_{i = 1}^{N}{w_{i}x_{i}}}} + \frac{\left( {{\alpha\; T} - \theta} \right)}{\alpha\; T}}}} & \left\lbrack {{Formula}\mspace{14mu} 6} \right\rbrack\end{matrix}$

Therefore, the multiply-accumulate result obtained by adding up productvalues (w_(i)*x_(i)) each obtained by multiplying the signal value x_(i)by the weight value w_(i) is given by the following expression.

$\begin{matrix}{{\sum\limits_{i = 1}^{N}{w_{i}x_{i}}} = {{\alpha\; R_{n}} - \frac{\left( {{\alpha\; T} - \theta} \right)}{\alpha\; T}}} & \left\lbrack {{Formula}\mspace{14mu} 7} \right\rbrack\end{matrix}$

That is, the multiply-accumulate result is a value obtained bysubtracting the constant defined by the charging speed α, the thresholdvalue θ, and the output period T from αR_(n)=α·(τ_(n)/T). In this way,the multiply-accumulate signal representing the multiply-accumulateresult can be output on the basis of the timing at which the voltageretained by the accumulation unit 11 exceeds the threshold value θ inthe output period T having the predetermined duration.

FIG. 7 is a schematic diagram showing a calculation example of amultiply-accumulate signal representing a total multiply-accumulateresult based on the multiply-accumulate results of both the positiveweight charges and the negative weight charges. In FIG. 7, themultiply-accumulate signal representing the multiply-accumulate resultof the positive weight charges is denoted by “S_(n) ⁺(t)” and its pulsewidth is denoted by “τ_(n) ⁺”. Moreover, the multiply-accumulate signalrepresenting the multiply-accumulate result of the negative weightcharges is denoted by “S_(n)(t)” and its pulse width is denoted by“τ_(n)”. Moreover, the multiply-accumulate signal representing the totalmultiply-accumulate result is denoted by “S_(n)(t)” and its pulse widthis denoted by “τ_(n)”.

The total amount V_(n) ⁺(t_(n)) of positive weight charge accumulated inthe capacitor 13 a at the end timing t_(n) of the input period T isgiven by the following expression. It should be noted that w_(i) ⁺represents a positive weight value.

$\begin{matrix}{{V_{n}^{+}\left( t_{n} \right)} = {T{\sum\limits_{i = 1}^{N^{+}}{w_{i}^{+}x_{i}}}}} & \left\lbrack {{Formula}\mspace{14mu} 8} \right\rbrack\end{matrix}$

The total amount V_(n) ⁻(t_(n)) of the negative weight chargeaccumulated in the capacitor 13 b at the end timing t_(n) of the inputperiod T is given by the following expression. It should be noted thatw_(i) ⁻ represents a negative weight value.

$\begin{matrix}{{V_{n}^{-}\left( t_{n} \right)} = {T{\sum\limits_{i = 1}^{N^{-}}{{w_{i}^{-}}x_{i}}}}} & \left\lbrack {{Formula}\mspace{14mu} 9} \right\rbrack\end{matrix}$

multiply-accumulate signal S_(n) ⁺(t) is R_(n) ⁺ (=τ_(n) ⁺/T), thepositive multiply-accumulate result obtained by adding up product values(w_(i) ⁺*x_(i)) obtained by multiplying the signal value x_(i) by thepositive weight value w_(i) ⁺ is given by the following expression. Itshould be noted that it is assumed that the threshold value θ is equalto or larger than the total amount V_(n) ⁺(t_(n)) of positive weightcharge.

$\begin{matrix}{{\sum\limits_{i = 1}^{N^{+}}{w_{i}^{+}x_{i}}} = {{\alpha\; R_{n}^{+}} - \frac{\left( {{\alpha\; T} - \theta} \right)}{\alpha\; T}}} & \left\lbrack {{Formula}\mspace{14mu} 10} \right\rbrack\end{matrix}$

25

In a case where the duty ratio of the negative multiply-accumulatesignal S_(n) ⁻(t) is R_(n) ⁻ (=τ_(n) ⁻/T), a negativemultiply-accumulate result obtained by adding up product values (|w_(i)⁻|*x_(i)) obtained by multiplying the input value x_(i) by the negativeweight value w_(i) ⁻ is given by the following expression. It should benoted that the charge speeda and the threshold value θ are equal to thevalues used in the expression (Formula 10). Moreover, it is assumed thatthe threshold value θ is equal to or larger than the total amount V_(n)⁻(t_(n)) of negative weight charge.

$\begin{matrix}{{\sum\limits_{i = 1}^{N^{-}}{{w_{i}^{-}}x_{i}}} = {{\alpha\; R_{n}^{-}} - \frac{\left( {{\alpha\; T} - \theta} \right)}{\alpha\; T}}} & \left\lbrack {{Formula}\mspace{14mu} 11} \right\rbrack\end{matrix}$

Therefore, with the expression (Formula 2) described above, the totalmultiply-accumulate result is given by the following expression.

$\begin{matrix}{{\sum\limits_{i = 1}^{N}{w_{i}x_{i}}} = {{\alpha\left( {R_{n}^{+} - R_{n}^{-}} \right)}\left( {= {\alpha\frac{\tau_{n}^{+} - \tau_{n}^{-}}{T}}} \right)}} & \left\lbrack {{Formula}\mspace{14mu} 12} \right\rbrack\end{matrix}$

That is, the total multiply-accumulate result is obtained by the chargespeed α, the pulse width τ_(n) ⁺ of the multiply-accumulate signal S_(n)⁺(t), the pulse width τ_(n) ⁻ of the multiply-accumulate signal S_(n)⁻(t), and the output period T. That is, it is possible to easilycalculate the multiply-accumulate result on the basis of the timingdetected by the comparator 22 a and the timing detected by thecomparator 22 b.

As shown in FIG. 7, it is possible to easily output themultiply-accumulate signal “S_(n)(t)” having the pulse width “τ_(n)” asthe multiply-accumulate signal representing the totalmultiply-accumulate result. It should be noted that it may be possibleto determine which one of the pulse width τ_(n) ⁺ of themultiply-accumulate signal S_(n) ⁺(t) and the pulse width τ_(n) ⁻ of themultiply-accumulate signal S_(n) ⁻(t) is larger. The multiply-accumulatesignal “S_(n)(t)” in a case where the pulse width τ_(n) ⁺ is larger canbe output as the positive multiply-accumulate signal and themultiply-accumulate signal “S_(n)(t)” in a case where the pulse widthτ_(n) ⁻ is larger can also be output as the negative multiply-accumulatesignal. A circuit for comparing the pulse width τ_(n) ⁺ with the pulsewidth τ_(n) ⁻ can be realized by using an AND circuit, a NOT circuit,and the like as appropriate.

A setting can also be made such that in a case where the ReLU function(ramp function) or the like is used, for example, when the positivemultiply-accumulate signal “S_(n)(t)” is obtained, the signal is outputas it is, and when the negative multiply-accumulate signal “S_(n)(t)” isobtained, 0 is output.

As the setting of the charging speeda and the threshold value θ, α=θ/ Tis set for the output period T. Accordingly, the constant determined bythe charge speed α, the threshold value θ, and the output period Tincluded in the expressions (Formula 6), (Formula 7), (Formula 10), and(Formula 11) can be set to be zero, and the processing can besimplified.

For example, the high-level value of the charge signal and theresistance value of the resistor 20 are set as appropriate to adjust thecharging speed α. The threshold value θ is set on the basis of theduration of the input period T. Accordingly, it is possible to exertadvantageous effects.

[Analog Circuit According to TACT Method]

FIG. 8 is a schematic circuit diagram showing an example of the analogcircuit 3 according to the TACT method. Pulse signals (TACT signals) areinput into the plurality of input signal lines 6 as input signals in₁ toin 6 at a timing corresponding to the signal value x_(i).

Here, a continuous pulse signal that rises to a timing corresponding tothe input value and keeps the ON level as illustrated in FIG. 2B isinput. Regarding the pulse signal, the duration of the ON time withrespect to the input period T corresponds to the input value in theinput period T. Hereinafter, the duration of the ON time in the inputperiod T will be referred to as a pulse width in the input period T insome cases.

At a timing at which the input period T elapses, the charges accumulatedin the capacitor 13 a are the sum total σ⁺ of the positive weightcharges each corresponding to the product value of the positive weightvalue w_(i) ⁺. Also, the charges accumulated in the capacitor 13 b arethe sum total o of the negative weight charges each corresponding to theproduct value of the negative weight value w_(i) ⁻.

Since the ON level of the electrical signal is maintained also after theinput period T ends, charges are accumulated in the capacitor 13 a andthe capacitor 13 b. A multiply-accumulate signal (PWM signal)representing the multiply-accumulate result of the positive weightcharges is generated on the basis of the timing at which the voltageretained by the capacitor 13 a exceeds the threshold value θ.

Moreover, a multiply-accumulate signal (PWM signal) representing themultiply-accumulate result of the negative weight charges is generatedon the basis of the timing at which the voltage retained by thecapacitor 13 b exceeds the threshold value θ. A multiply-accumulatesignal representing the total multiply-accumulate result can begenerated on the basis of these positive and negativemultiply-accumulate signals.

In the analog circuit 3 according to the TACT method shown in FIG. 8,the output period T corresponds to the charging period. Moreover, theinput signals ini to in 6 input into the plurality of input signal lines6 in the output period T corresponds to the charge signal.

Therefore, the analog circuit 3 according to the TACT method illustratedin FIG. 8, the same charge signal is supplied to the capacitors 13 a and13 b via the plurality of input signal lines 6. Although not shown inthe figure, a configuration for inputting the input signals in₁ to in₆into the plurality of input signal lines 6 during the output period Tcorresponds to the charging unit 15. Accordingly, the configuration forinputting the input signals in₁ to in₆ also functions as the chargingunit 15. As shown in FIG. 8, it is also possible to consider theplurality of input signal lines 6 itself as a part of the charging unit15.

Here, the inventor has considered the time constant as a parameterassociated with the accumulation of charges of the capacitor 13 in theinput period T and the output period (charging period) T. Hereinabove,the accumulation of charges in the input period T and the output periodT is approximated as a linear change and described using the “slopew_(i)” and the “slope α” as shown in FIG. 6. As a matter of course, theanalog-type arithmetic apparatus 100 capable of accurately performingpredetermined arithmetic processing including the multiply-accumulateoperation can be realized on the basis of such an approximation.

On the other hand, it is considered that the charges (potential) of thecapacitor 13 are accumulated in accordance with the time constantdetermined by the circuit configuration of the analog circuit 3 shown inFIGS. 5 and 8 in the input period T and the output period (chargingperiod) T. Therefore, the inventor thought that a more accuratemultiply-accumulate operation could be achieved on the basis of theaccumulation of charges according to the time constant by designing thecircuit configuration as appropriate.

Hereinafter, the charges (potential) of the capacitor 13 will besometimes described as the (charges) potential of the output line 7 foroutputting charges to the capacitor 13.

The inventor found a configuration that makes the time constant for theoutput lines 7 irrespective of the number of resistors 17 disposedbetween the output lines 7 and the plurality of input signal lines 6.

First, it is assumed that the capacitors 13 a and 13 b functionallyinclude a parasitic capacitance (not shown) generated in the outputlines 7 a and 7 b. In this case, a minimum value of the capacitance thatcan be taken by the capacitors 13 a and 13 b is a parasitic capacitancegenerated in the output lines 7. For example, even in a case where thecapacitors 13 are not provided, charges are accumulated on the basis ofthe parasitic capacitance generated in the output lines 7 a and 7 b anda multiply-accumulate signal can be generated on the basis of thethreshold determination. The same applies to the analog circuit 3according to the PWM method illustrated in FIG. 5.

The time constant of the output lines 7 sequentially changes inaccordance with the number of input signals sequentially input over timeand the number of resistors 17 (on-resistances) in a state capable oftransmitting a signal to the output lines 7. Here, the focus is placedon the time constant at the end of the input period T. In the analogcircuit 3 according to the TACT method according to this embodiment,signals are input into all of the input signal lines 6 at the end of theinput period T. Therefore, the number of input signals at the end of theinput period T takes a maximum value and a constant value. As a result,the time constant at the end of the input period T sequentially changesin accordance with the number of on-resistances.

Here, the resistance values of the resistors 17 are set to be the sameresistance value R. In other words, a binary connect configuration isemployed. Moreover, the parasitic capacitance of each synapse circuit 8is designed to be a constant capacitance C. Since the resistors 17 areconnected in parallel to one output line 7, the combined resistance isR/N in a case where N resistors 17 are connected (the number ofon-resistances is N). On the other hand, since the number of synapsecircuits 8 is N which is equal to the number of resistors 17, thecombined capacitance is NC.

For example, a multiply-accumulate signal is generated on the basis ofthe parasitic capacitance of each synapse circuit 8 without providingthe capacitors 13. In this case, the value of the combined resistance xcombined capacitance is RC irrespective of the number of resistors 17(number of on-resistances). Therefore, the time constant of the outputlines 7 at the end of the input period T is also RC irrespective of thenumber of resistors 17.

In a case where the capacitors 13 are installed, the capacitance of thecapacitors 13 is set to a value (number of resistors 17×C₀) obtained bymultiplying a predetermined constant Co by the number of resistors 17(number of on-resistances). Accordingly, the time constant isR/N×(NC+NC₀)=R×(C+C₀) and is constant irrespective of the number ofresistors 17. Thus, the time constant can be made constant irrespectiveof the number of resistors 17.

Therefore, the potential V of each output line 7 at the end of the inputperiod T can be approximated by the following expression.

$\begin{matrix}{V = {V_{c}\left( {1 - e^{- \frac{t_{ave}}{R \cdot C}}} \right)}} & \left\lbrack {{Formula}\mspace{14mu} 13} \right\rbrack\end{matrix}$

FIG. 9 is a schematic graph for describing the potential V of eachoutput line 7 at the end of the input period T. The potential V of eachoutput line 7 at the end of the input period T will be described withreference to the expression (Formula 13) and FIG. 9. It should be notedthat the time constant curve in the graph of FIG. 9 is a curvecorresponding to the expression (Formula 13).

“Vc” represents a constant and is a value corresponding to theconvergence value of the potential after a time equal to or longer thanthe time constant has elapsed.

“t_(ave)” represents the average of pulse widths of the pulse signalsinput into the input signal lines 6 within the input period T.

It should be noted that the change in the charge of each output line 7until the end of the input period T does not always occur in accordancewith the time constant curve shown in FIG. 9. It was found that at leastthe potential V of each output line 7 at the end of the input period Tcan be approximated by the expression (Formula 13).

On the other hand, in the output period (charging period) T, the inputsignals ini to in 6 (charge signals) at the ON level are input into allthe input signal lines 6. Therefore, it can be considered that thechange in charge in the output period (charging period) T is performedin accordance with the time constant curve shown in FIG. 9.

Here, it is assumed that the potential V of each output line 7 at theend timing t_(n) of the input period T, which is approximated by theexpression (Formula 13), is denoted by “Vt_(n)”. Moreover, the time fromthe end timing t_(n) of the input period T (time within the outputperiod T) is set to t. Then, the potential “V_(out)” of each output line7 in the output period T can be approximated by the following equation.

$\begin{matrix}{V_{out} = {V_{t_{n}} + {\left( {V_{in} - V_{t_{n}}} \right)\left( {1 - e^{- \frac{t}{R \cdot C}}} \right)}}} & \left\lbrack {{Formula}\mspace{14mu} 14} \right\rbrack\end{matrix}$

Here, as shown in FIG. 9, the input period T and the threshold value θare determined in accordance with the time constant curve correspondingto the expression (Formula 13). That is, the potential V when the inputperiod T is substituted for “t_(ave)” of (Formula 13) is set as thethreshold value θ. Accordingly, in a case where the maximum pulses whosepulse width in the input period T is maximum are input into all theinput signal lines 6, the potential of the output line 7 exceeds thethreshold value at the end timing of the input period T (start timing ofthe output period T).

On the other hand, in a case where the pulses whose pulse width in theinput period T is 0 are input into all the input signal lines 6, thepotential of the output line 7 exceeds the threshold value at the endtiming of the output period T. As a result, it is possible to accuratelycalculate the multiply-accumulate signal with high resolution within theoutput period T. That is, by setting the threshold value θ on the basisof the duration of the input period T, an advantageous effect can beexhibited.

As shown in FIG. 9, the threshold determination is performed on each ofthe capacitors 13 a and 13 b on the basis of the threshold value θ.Accordingly, the multiply-accumulate signal “S_(n)(t)” using “t_(ave)”that is the average of the pulse widths of the respective pulse signalsin the input period T as the pulse width “τ_(n)” can be generated andoutput accurately. Thus, it was found that the pulse width “τ_(n)” ofthe multiply-accumulate signal “S_(n)(t)” can also be approximated bythe expression (Formula 13).

Irrespective of how the number of resistors 17 for connecting the inputsignal lines 6 and the positive charge output line 7 a (i.e., the numberof positive weight multiplication units), and the number of resistors 17for connecting the input signal lines 6 and the negative charge outputline 7 b (i.e., the number of negative multiplication units) arecombined in each analog circuit 3, the multiply-accumulate operationillustrated in FIG. 9 is realized for the potential V⁺ of the positivecharge output line 7 a and the potential V⁻ of the negative chargeoutput line 7 b.

Therefore, as illustrated in FIG. 7, the multiply-accumulate signal“S_(n)(t)” representing the total multiply-accumulate result can becalculated on the basis of the pulse width τ_(n) ⁺ of themultiply-accumulate signal S_(n) ⁺(t) and the pulse width τ_(n) ⁻ of themultiply-accumulate signal S_(n) ⁻(t).

It should be noted that even in a case where other configurations areemployed, the analog circuit 3 is designed such that the time constantof the positive charge output line 7 a is equal to the time constant ofthe negative charge output line 7. Thus, the multiply-accumulateoperation illustrated in FIG. 9 is realized with respect to thepotential V⁺ of the positive charge output line 7 a and the potential V⁻of the negative charge output line 7 b.

As a matter of course, the present technology is not limited to the casewhere the binary connect configuration is employed in which the positiveweight value wi⁺ and the absolute value of the negative weight value wi⁻are fixed to the same value.

For example, the positive weight value wi⁺ and the absolute value of thenegative weight value wi⁻ are multivalued. That is, the positive weightvalue wi⁺ and the absolute value of the negative weight value wi⁻ areset to any of the plurality of values different from each other.Alternatively, the positive weight value wi⁺ and the absolute value ofthe negative weight value wi⁻ are randomly set.

Also in such a case, the analog circuit 3 is designed such that the timeconstant of the positive charge output line 7 a is equal to the timeconstant of the negative charge output line 7. Thus, themultiply-accumulate operation described shown in FIG. 9 is realized withrespect to the potential V⁺ of the positive charge output line 7 a andthe potential V⁻ of the negative charge output line 7 b.

In the present disclosure, the time constant of the output line 7 isincluded in a time constant associated with the output of the chargecorresponding to the product value to the output line 7 by the pluralityof synapse circuits 8. The time constant of the positive charge outputline 7 a is included in the time constant associated with the output ofthe positive charge to the positive charge output line 7 a by theplurality of positive weight multiplication units 8 a. The time constantof the negative charge output line 7 b is included in the time constantassociated with the output of the weight charge to the negative chargeoutput line 7 b by the plurality of weight multiplication units 8 b.

Next, consider in the analog circuit 3 according to the PWM methodillustrated in FIG. 5. In the analog circuit 3 according to the PWMmethod illustrated shown in FIG. 5, the input signals ini to in 6 areinput into the plurality of input signal lines 6 in the input period T.Then, the charge signal CH is input via the charging line 19 in theoutput period T.

Here, the potential V of the output line 7 at the end of the inputperiod T can be approximated by the expression (Formula 13) as in theTACT method. That is, as shown in FIG. 9, it can be approximated by thetime constant curve according to the time constant of the output line 7.Thereafter, the charging line 19 and the resistance value of theresistor 20 are designed such that the charging by the charging unit 15is performed in accordance with the same time constant curve.Accordingly, the multiply-accumulate operation illustrated in FIG. 9 isrealized.

For example, in the configuration shown in FIG. 5, the combinedresistance of the positive resistor 17 a and the resistance value of theresistor 20 a connected to the charging line 19 are made to equal.Accordingly, the multiply-accumulate operation illustrated in FIG. 9 isrealized with respect to the positive charge output line 7 a. Moreover,the combined resistance of the negative resistor 17 b and the resistancevalue of the resistor 20 b connected to the charging line 19 are made toequal. Accordingly, the multiply-accumulate operation illustrated inFIG. 9 is realized with respect to the negative charge output line 7 b.

For example, the analog circuit 3 is designed such that the timeconstant of the positive charge output line 7 a and the time constant ofthe negative charge output line 7 b in the input period T are equal.Then, the combined resistance of the positive resistor 17 a and theresistance value of the resistor 20 a are made to equal and the combinedresistance of the negative resistor 17 b and the resistance value of theresistor 20 b are made to equal.

Thus, the multiply-accumulate operation illustrated in FIG. 9 isrealized in accordance with the same time constant with respect to thepotential V⁺ of the positive charge output line 7 a and the potential V⁻of the negative charge output line 7 b. As a result, themultiply-accumulate signal “S_(n)(t)” having, as the pulse width“τ_(n)”, the average of the pulse widths of the respective pulse signalsin the input period T can be accurately generated and output.

As a matter of course, the application of the present technology is notlimited to the case where the multiply-accumulate operation illustratedin FIG. 9 is realized. Other configurations and othermultiply-accumulate operation may be performed as the analog circuit 3according to the PWM method and the analog circuit 3 according to theTACT method. In any case, the result of the multiply-accumulateoperation can be obtained on the basis of the potential of the positivecharge output line 7 a (the voltage retained in the capacitor 13 a) V⁺and the potential of the negative charge output line 7 b (the voltageretained in the capacitor 13 b) V⁻.

In this embodiment, the analog circuit 3 according to the PWM method andthe analog circuit 3 according to the TACT method both include theplurality of input signal lines 6, the plurality of synapse circuits 8,the accumulation unit 11, the charging unit 15, and the signal outputunit 12.

The accumulation unit 11 includes the capacitor 13 a capable ofaccumulating the positive weight charge generated by the synapse circuit(positive weight multiplication unit) 8 a and the capacitor 13 b capableof accumulating the negative weight charge generated by the synapsecircuit (negative weight multiplication unit) 8 b.

The charging unit 15 charges the capacitors 13 a and 13 b after theinput period T. The signal output unit 12 can output themultiply-accumulate signal by performing threshold determination usingthe predetermined threshold value on each of the capacitors 13 a and 13b. It should be noted that the predetermined threshold value may be seton the basis of the duration of the input period.

FIGS. 10 to 13 are schematic diagrams each showing an example of theconfiguration of the arithmetic apparatus 100.

The arithmetic apparatus 100 illustrated in FIGS. 10 to 13 includes theplurality of input signal lines 6 and the plurality of analog circuits 3connected in parallel to the plurality of input signal lines 6. Byemploying such a configuration, it is possible to input an electricalsignal in parallel into each analog circuit 3 and it is possible toincrease the arithmetic processing speed. As a result, it is possible toexhibit excellent operation performance.

In the arithmetic apparatus 100 illustrated in FIGS. 10 and 11, theanalog circuits 3 according to the PWM method described with referenceto FIGS. 5 to 7 are arranged as a plurality of analog circuits 3. In thearithmetic apparatus 100 illustrated in FIGS. 12 and 13, the analogcircuits 3 according to the TACT method described with reference toFIGS. 8 and 9 are arranged as the plurality of analog circuits 3.

In this embodiment, charging by the charging unit 15 is performed on theplurality of analog circuits 3 on a common charging mode. Moreover, acommon threshold value is set as the predetermined threshold value usedfor the threshold determination by the signal output unit 12 in theneuron circuit 9. That is, the charging is performed on the samecharging mode in each analog circuit 3 and the threshold determinationis performed using the same threshold value.

In the analog circuit 3, the common charging mode is performed on eachof the capacitors 13 a and 13 b. That is, the charging is performed onthe plurality of capacitors 13 a and 13 b included in the plurality ofanalog circuits 3 on the common charging mode. Then, the thresholddetermination is performed at the plurality of analog circuits 3 byusing the common threshold value, and the multiply-accumulate signal isoutput.

The common charging mode can be charging for supplying the charge signalin each analog circuits 3 in a common charging period. Moreover, thecommon charging mode also includes a mode on which the same chargesignal is supplied in each analog circuit 3. Also, the common chargingmode includes charging at a common charging speed (charging rate),charging according to a common time constant, and the like. As a matterof course, the present technology is not limited thereto.

For example, as shown in FIGS. 10 and 11, a common charging line 19 isarranged for the plurality of analog circuits 3. The charging line 19 isarranged to be parallel to the plurality of input signal lines 6. Theresistor 20 a is connected between the charging line 19 and the positivecharge output line 7 a of each analog circuit 3. The resistor 20 b isconnected between the charging line 19 and the negative charge outputline 7 b of each analog circuit 3.

The charge signal that becomes ON level during the output period(charging period) T is input via the charging line 19. Thus, it ispossible to supply the same charge signal in the common charging period.Resistors all having the same resistance value are arranged as theresistors 20 a and 20 b. Thus, it is possible to perform charging at thecommon charging rate in the common charging speed.

For example, it is assumed that charging at the common charging speed isperformed in the common charging period. In this case, the potential ofthe positive charge output line 7 a and the potential of the negativecharge output line 7 b of each analog circuit 3 rise in accordance withthe charging speed a as illustrated in FIG. 6.

Thus, as illustrated in FIG. 7, the multiply-accumulate signal“S_(n)(t)” representing the total multiply-accumulate result can becalculated on the basis of the pulse width T_(n) ⁺ of themultiply-accumulate signal S_(n) ⁺(t) and the pulse width τ_(n) ⁻ of themultiply-accumulate signal S_(n) ⁻(t) in each analog circuit 3.

Moreover, each analog circuit 3 and the charging unit 15 are designedsuch that the time constant of each output line 7 (the positive chargeoutput line 7 a or the negative charge output line 7 b) in the outputperiod T is a common value. In this case, it is possible to realizecharging according to the common time constant.

Each analog circuit 3 is designed such that the time constant of thepositive charge output line 7 a and the time constant of the negativecharge output line 7 b in the input period T in each of the plurality ofanalog circuits 3 are equal and that the value of the time constant is acommon value in all the analog circuits 3. Then, the charging unit 15 isdesigned such that the time constant of the positive charge output line7 a and the time constant of the negative charge output line 7 b in theoutput period T are equal to the time constant in the input period T.Accordingly, the multiply-accumulate operation illustrated in FIG. 9 isrealized in each analog circuit 3. It should be noted that the thresholdvalue is determined on the basis of the input period T in accordancewith the time constant curve and is set as a common threshold value.

Moreover, as shown in FIGS. 12 and 13, an input signal is input suchthat the ON state is maintained in the output period T. Accordingly,charging in which the same charge signal is supplied during the commoncharging period is performed.

Moreover, each analog circuit 3 and the charging unit are designed suchthat the time constant of each output line 7 (positive charge outputline 7 a, negative charge output line 7 b) is a common value. In thiscase, it is possible to realize charging according to the common timeconstant. Accordingly, the multiply-accumulate operation illustrated inFIG. 9 can be realized in each analog circuit 3. It should be noted thatthe threshold value is determined on the basis of the input period T inaccordance with the time constant curve and is used as a commonthreshold value.

Here, the inventor has further considered the output of themultiply-accumulate signal by the analog circuit 3 when the chargingaccording to the common charging mode is performed and when thethreshold determination using the common threshold value is performed.Then, the inventor found that the accuracy of the multiply-accumulateoperation is improved by outputting the multiply-accumulate signal asappropriate from each analog circuit 3 in a common output period T. Inother words, the inventor found that the accuracy of themultiply-accumulate operation is improved by increasing the number ofanalog circuits capable of outputting the multiply-accumulate signal inthe common output period T.

For example, it is assumed that the binary connect configuration isemployed in the arithmetic apparatus 100 illustrated in FIGS. 10 and 11.In binary connects, the positive weight value and the absolute value ofthe negative weight are fixed to the same value. That is, the resistancevalues of the resistors 17 are all fixed to the same value.

In the configuration shown in FIG. 10, the sum of the number of positiveresistors 17 a and the number of negative resistors 17 b is set to acommon value (seven) at each analog circuit 3. Therefore, with theconfiguration shown in FIG. 10, in the plurality of analog circuits 3, avalue obtained by adding a sum total of the positive weight values(hereinafter, referred to as positive sum total value) set at theplurality of synapse circuits 8 and a sum total of the absolute valuesof the negative weight values (hereinafter, referred to as negative sumtotal value) set at the plurality of synapse circuits 8 is a commonvalue.

It should be noted that the value obtained by adding the positive sumtotal value and the negative sum total value corresponds to a sum totalof the absolute values of the weight values set in the plurality ofsynapse circuits 8, and will be hereinafter referred to as a weight sumtotal value.

In the configuration shown in FIG. 11, the sum of the number of positiveresistors 17 a and the number of negative resistors 17 b is not set to acommon value at each analog circuit 3. For example, the total number ofresistors 17 may be set to any of a plurality of numbers different fromeach other. Alternatively, the total number of resistors 17 may berandomly set.

Therefore, with the configuration shown in FIG. 11, in the plurality ofanalog circuits 3, the value (weight sum total value) obtained by addingthe positive sum total value and the negative sum total value is not acommon value. For example, it is possible to realize a configuration inwhich the sum total weight value is any of a plurality of valuesdifferent from each other. Alternatively, it is also possible to realizea configuration in which the sum total weight value is a random value.

It should be noted that in the configuration shown in FIG. 11, there issynapse circuits 8 in which both the positive resistor 17 a and thenegative resistor 17 b are not set. It can be said that such a synapsecircuit 8 is a multiplication unit corresponding to a term where theweight value is zero in the multiply-accumulate operation.

Regarding the configurations shown in FIGS. 10 and 11, it is assumedthat configurations other than the binary connect are employed. Thepositive weight value and the absolute value of the negative weightvalue are multivalued. Alternatively, the positive weight value and theabsolute value of the negative weight value are randomly set.

As for the value (weight sum total value) obtained by adding thepositive sum total value and the negative sum total value, any of aconfiguration in which such a value is a common value, a configurationin which such a value is any of a plurality of values different fromeach other, and a configuration in which such a value is a random valuecan be realized.

For example, the arithmetic apparatus 100 illustrated in FIGS. 10 and 11can be realized using as appropriate the resistors 17 having multivaluedresistance values or the resistors 17 having random resistance values onthe condition that the weight sum total value is a common value or theweight sum total value is any of the plurality of values different fromeach other.

The same applies to the arithmetic apparatus 100 illustrated in FIGS. 12and 13. For example, in a case where the binary connect configuration isemployed, with the configuration shown in FIG. 12, the weight sum totalvalue is a common value in the plurality of analog circuits 3. With theconfiguration shown in FIG. 13, the weight sum total value is not acommon value in the plurality of analog circuits 3. For example, it ispossible to realize a configuration in which the sum total weight valueis any of the plurality of values different from each other.Alternatively, it is also possible to realize a configuration in whichthe sum total weight value is a random value.

Regarding the configurations shown in FIGS. 12 and 13, it is assumedthat configurations other than the binary connect are employed. In thiscase, any of a configuration in which the weight sum total value is acommon value, a configuration in which the weight sum total value is anyof the plurality of values different from each other, and aconfiguration in which the weight sum total value is a random value canbe realized.

The charging according to the common charging mode and the thresholddetermination using the common threshold value are performed on themulti-input x multi-output arithmetic apparatus 100 having such variousconfigurations, to thereby cause each analog circuit 3 to properlyoutput the multiply-accumulate signal. For that, the inventor hasfocused on the weight sum total value, the positive sum total value, andthe negative sum total value in each analog circuit 3.

Then, the inventor newly devised to perform charging on the basis of amaximum value of the weight sum total value among the plurality ofanalog circuits 3 and to perform threshold determination using athreshold value based on the maximum value of the weight sum total valueamong the plurality of analog circuits 3. That is, the inventor newlydevised a technology of performing charging on the basis of the maximumvalue among the weight sum total values in the plurality of analogcircuits 3 and performing threshold determination using a thresholdvalue based on the maximum value.

For example, in the configurations shown in FIGS. 10 and 11, thecombined resistance in a case of connecting all the resistors 17included in the analog circuit 3 whose weight sum total value is themaximum in parallel is used as a common resistance value. Then, theresistance values of all the resistors 20 a and 20 b are unified intothat common resistance value. In this case, charging according to thecommon time constant is realized in the output period T.

This charging corresponds to charging in which the time constantassociated with the output of the charges corresponding to the productvalues to the output line 7 by the plurality of synapse circuits 8 whoseweight sum total value is the maximum value is used as the common timeconstant.

[0 0 6 4] The threshold value is determined on the basis of the inputperiod T in accordance with the time constant curve commonly defined bythe resistance value. Thus, it is possible to cause each analog circuit3 to output the multiply-accumulate signal in the common output periodT. Accordingly, it is possible to improve the accuracy of themultiply-accumulate operation. It should be noted that the thresholdvalue corresponds to the threshold value based on the maximum value.

Moreover, the inventor newly devised to perform charging based on themaximum value among the positive sum total values and the negative sumtotal values in the plurality of analog circuits 3 and to performthreshold determination using a threshold value based on the maximumvalue among the positive sum total values and the negative sum totalvalues in the plurality of analog circuits 3. That is, the inventordevised to compare the positive sum total value and the negative sumtotal value of each analog circuit 3 over all the plurality of analogcircuits 3, perform charging on the basis of the maximum value amongthem, and perform threshold determination using the threshold valuebased on the maximum value.

Here, the maximum value among the positive sum total values and thenegative sum total values in the plurality of analog circuits 3 isdefined as a maximum sum total value.

The positive weight charge or the negative weight charge related to themaximum sum total value is defined as a maximum weight charge. Forexample, it is assumed that the positive sum total value of one of theanalog circuits 3 of the plurality of analog circuits 3 is the maximumsum total value. In the input period T, the positive weight chargeoutput from the positive charge output line 7 a in that analog ciruit 3is the maximum weight charge.

Alternatively, it is assumed that the negative sum total value of oneanalog circuit 3 is the maximum sum total value. In the input period T,the negative weight charge output from the negative charge output line 7b in that analog circuit 3 is the maximum weight charge.

It should be noted that the maximum weight charge is a parameterunrelated to the level or the like of the input signal. That is,regardless of what signal is input as the input signal, the positiveweight charge or the negative weight charge output from the positiveweight output line or the negative weight output line, which is themaximum sum total value, is the maximum weight charge.

The positive charge output line or the negative charge output line fromwhich the maximum weight charge is output is defined as a maximum chargeoutput line.

In the configurations shown in FIGS. 12 and 13, the combined resistanceof the resistors 17 connected to the maximum charge output line is usedas a common resistance value. Then, the resistance values of all theresistors 20 a and 20 b are unified into that common resistance value.In this case, charging according to the common time constant is realizedin the output period T. It should be noted that the combined resistanceof the resistors 17 connected to the maximum charge output line is aparameter corresponding to the maximum sum total value.

This charging corresponds to charging in which the time constantassociated with the output of the maximum weight charge to the maximumcharge output line is used as the common time constant.

The threshold value is determined on the basis of the input period T inaccordance with the time constant curve commonly defined by theresistance value. Thus, it is possible to cause each analog circuit 3 tooutput the multiply-accumulate signal in the common output period T.Accordingly, it is possible to improve the accuracy of themultiply-accumulate operation. It should be noted that the thresholdvalue corresponds to a threshold value based on the maximum sum totalvalue.

It should be noted that it is assumed that the weight sum total value ofthe analog circuit 3 in which all resistors 17 are connected to only oneof the positive charge output line or the negative charge output line isa maximum value in the plurality of analog circuits 3. In this case, themaximum value of the weight sum total value is also the maximum sumtotal value that is the maximum value among the positive sum totalvalues and the negative sum total values. Therefore, the charging isperformed on the same charging mode and the threshold determination isperformed by using the same threshold value.

In the configurations shown in FIGS. 12 and 13, the threshold value isset in accordance with the time constant curve in a case of inputtingthe charge signal in the output period T into the output line to whichall the resistors 17 included in the analog circuit 3 whose weight sumtotal value is the maximum value are connected in parallel. It should benoted that the output line to which all of the resistors 17 included inthe analog circuit 3 whose weight sum total value is the maximum valueare connected in parallel is not always present in practice.

By setting such a threshold value, the multiply-accumulate signal can beoutput in each analog circuit 3 during the common output period T.Accordingly, it is possible to improve the accuracy of themultiply-accumulate operation. It should be noted that the thresholdvalue corresponds to the threshold value based on the maximum value.

Moreover, the threshold value is set to the maximum charge output linein accordance with the time constant curve in a case of inputting thecharge signal in the output period T. Thus, the multiply-accumulatesignal can be output in each analog circuit 3 during the common outputperiod T. As a result, it is possible to improve the accuracy of themultiply-accumulate operation. It should be noted that the thresholdvalue corresponds to the threshold value based on the maximum sum totalvalue.

It should be noted that it is assumed that the weight sum total value ofthe analog circuit 3 in which all resistors 17 are connected to only oneof the positive charge output line or the negative charge output line isa maximum value in the plurality of analog circuits 3. In this case, themaximum value of the weight sum total value is also the maximum sumtotal value that is the maximum value among the positive sum totalvalues and the negative sum total values. Therefore, the thresholddetermination is performed at the same threshold value.

As a matter of course, the present technology is not limited to suchcharging mode and setting of the threshold value. Any configuration andmethod for realizing the charging according to the common charging modeand the threshold determination using the common threshold value may beemployed. Moreover, those may be combined with the configuration and themethod or the like for realizing the multiply-accumulate operationillustrated in FIG. 9 described above.

FIG. 14 is a schematic diagram showing a configuration example of theneural network. For example, as shown in FIG. 14, a neural network isrealized by performing a plurality of multiply-accumulate operations, aplurality of normalization processes, and a plurality of poolingprocesses.

Here, the multiply-accumulate operation corresponds to the output of aplurality of multiply-accumulate results by the arithmetic apparatus 100including the plurality of analog circuits 3. The normalizationprocessing is processing of normalizing the input signal for the inputof the multiply-accumulate operation at the next stage. The poolingprocessing is processing of reducing the number of input signals inaccordance with the number of inputs of the multiply-accumulateoperation at the next stage. By the normalization processing and thepooling processing, it is possible to simplify the processing andshorten the processing time.

It should be noted that in FIG. 14, a case where the arithmeticapparatus 100 that performs each of multiply-accumulate operations 1 to8 is constituted by the plurality of analog circuits 3 designed with acommon time constant is shown. That is, the charging according to thecommon time constant is performed on the common charging mode in eacharithmetic apparatus 100.

In each arithmetic apparatus 100, the common input period T and thecommon threshold value θ are set on the basis of the common timeconstant curve. On the other hand, in the example shown in FIG. 14,different input periods T and different threshold values are set todifferent arithmetic apparatuses 100. The present technology is notlimited thereto, and the common input period T and the common thresholdvalue θ may be set to all the arithmetic apparatuses 100.

As a matter of course, the arithmetic apparatus 100 is constituted bythe analog circuits 3 each having another configuration and themultiply-accumulate operations may be performed. Also in this case, itis possible to realize efficient and high-speed arithmetic processing bysetting the common charging mode and the common threshold value in eachanalog circuit 3.

As described above, in the arithmetic apparatus 100 according to thisembodiment, the common charging mode is performed and the commonthreshold value is set with respect to the one or more analog circuits3. Accordingly, it is possible to realize efficient and high-speedarithmetic processing in the analog circuit that performs themultiply-accumulate operation. That is, by arranging a plurality of setsof the plurality of analog circuits 3 in parallel, simultaneous paralleloperations can be performed at a time by one-time input, and high-speedoperation and efficient operation are realized.

Other Embodiments

The present technology is not limited to the embodiment described above,and various other embodiments can be realized.

FIG. 15 is a schematic circuit diagram showing another example of theanalog circuit 3 according to the PWM method. In the analog circuit 3illustrated in FIG. 15, two current sources 25 a and 25 b are providedas the charging unit 15.

The current source 25 a is connected to the side (side opposite to theGND) of the capacitor 13 a, which is connected to the positive chargeoutput line 7 a, via a switch 16 c. The current source 25 b is connectedto the side (side opposite to the GND) of the capacitor 13 b, which isconnected to the negative charge output line 7 b, via a switch 16 d.

In the analog circuit 3 illustrated in FIG. 15, the capacitors 13 a and13 b are charged at the same charging speed by the current sources 25 aand 25 b. Accordingly, the potential V⁺ of the positive charge outputline 7 a (the voltage retained by the capacitor 13 a) and the potentialV⁻ of the negative charge output line 7 b (the voltage retained by thecapacitor 13 b) are each increased. The specific configuration of thecurrent source 25 is not limited, and may be arbitrarily designed.

Even in a case where such a configuration is employed, the chargingaccording to the common charging mode and the threshold determinationusing the common threshold value can be performed on one or more analogcircuits 3. For example, in a case of arranging the plurality of analogcircuits 3 in parallel, the charging according to the common chargingmode and the threshold determination using the common threshold value isperformed. Accordingly, it is possible to realize efficient andhigh-speed arithmetic processing.

FIG. 16 is a schematic circuit diagram showing another example of theanalog circuit 3 according to the PWM method. FIG. 17 is a diagram fordescribing an example of calculation of the multiply-accumulate signalby the analog circuit 3 shown in FIG. 16.

In the analog circuit 3 illustrated in FIG. 16, a differentialamplification circuit 26 outputs a charge (V⁺−V⁻) corresponding to thedifference between the total amount of positive weight charge and thetotal amount of negative weight charge and the charge (V⁺−V⁻) is storedin the capacitor 13 included in the accumulation unit 11. The specificconfiguration of the differential amplification circuit 26 is notlimited, and may be arbitrarily designed.

At the start timing of the input period T, switches 16 a, 16 b, and 16 care turned on and the switch 16 b is turned off. Then, the input signalis input within the input period T. The charge (V⁺−V⁻) output by thedifferential amplification circuit 26 is accumulated in the capacitor13. It should be noted that the illustration of the charge accumulationstate in the input period T is omitted from FIG. 17.

At the end timing t_(n) of the input period T, the switch 16 c is turnedoff and the switch 16 d is turned on. Then, as shown in FIG. 17,charging by the charging unit 15 (current source 25) is started at theend timing t_(n) of the input period T.

Moreover, the comparator 22 of the signal output unit 12 detects thetiming at which the voltage retained by the capacitor 13 exceeds thethreshold value θ. Based on the detected timing, the signal generationunit 23 calculates the multiply-accumulate signal (PWM signal)“S_(n)(t)”.

Thus, the multiply-accumulate signal “S_(n)(t)” can be output byperforming the threshold determination on the charge corresponding tothe difference (V⁺−V⁻) between the total amount of positive weightcharge and the total amount of negative weight charge. Also, thecharging according to the common charging mode and the thresholddetermination using the common threshold value can be performed on theone or more analog circuits 3. For example, in a case of arranging theplurality of analog circuits 3 in parallel, the charging according tothe common charging mode and the threshold determination using thecommon threshold value are performed. Accordingly, it is possible torealize efficient and high-speed arithmetic processing.

In the above description, the case where the plurality of analogcircuits is arranged in parallel has been mainly described. The presenttechnology is not limited thereto, and can also be applied to a singleanalog circuit. For example, a positive weight value accumulation unitand a negative weight accumulation unit are charged on the commoncharging mode. Then, the threshold determination is performed on thepositive weight charge and the negative weight charge by using thecommon threshold value. Accordingly, it is possible to realize efficientand high-speed arithmetic processing.

In the above description, the case of outputting the multiply-accumulatesignal on the basis of the timing at which the voltage retained by theaccumulation unit increases beyond the threshold value has beenexemplified. However, a configuration to output the multiply-accumulatesignal on the basis of the timing at which the voltage retained by theaccumulation unit decreases beyond the threshold voltage may beemployed. For example, charging is performed in advance until thevoltage of the capacitor that functions as the accumulation unit reachesa predetermined preset value. After the sum of charges eachcorresponding to the product value of the signal value and the weightvalue is accumulated, the capacitor is discharged at a predeterminedrate. In such a case, the multiply-accumulate signal can be output onthe basis of a timing at which the voltage retained by the capacitordecreases beyond the threshold value. As a matter of course, the presenttechnology is not limited to such a configuration. It should be notedthat in the present disclosure, discharging the capacitor is included incharging the capacitor with negative charges.

In the above description, the case where the pair of output lines isused has been described. The present technology is not limited thereto,and three or more output lines may be provided. That is, the presenttechnology described above can be applied also in a case where one ormore any number of output lines are used. For example, themultiplication unit includes a resistor that is connected between anassociated input line and any one of the one or more output lines anddefines a weight value, and outputs a charge corresponding to theproduct value to the output line to which the resistor is connected. Asa matter of course, the present technology is not limited thereto.

The configurations of the arithmetic apparatus, the multiply-accumulatedevices, the analog circuits, the synapse circuits, the neuron circuits,and the like, the method of generating the multiply-accumulate signal,and the like described above with reference to the drawings belong tomerely an embodiment, and can be arbitrarily modified without departingfrom the gist of the present technology. That is, any otherconfigurations, methods, and the like for carrying out the presenttechnology may be employed.

In the present disclosure, “the same”, “equal”, “orthogonal”,“parallel”, and the like are concepts including “substantially thesame”, “substantially equal”, “substantially orthogonal”, “substantiallyparallel”, and the like. For example, the states included in apredetermined range (e.g., a range of ±10%) with reference to“completely the same”, “completely equal”, “completely orthogonal”,“completely parallel”, and the like are also included.

At least two of the features of the present technology described abovecan also be combined. In other words, various features described in therespective embodiments may be combined discretionarily irrespective ofthe embodiments. Moreover, the various effects described above are notlimitative but are merely illustrative, and other effects may beprovided.

It should be noted that the present technology can also take thefollowing configurations.

-   (1) An arithmetic apparatus, including:

a plurality of input lines into each of which an electrical signalcorresponding to an input value is input within a predetermined inputperiod; and

one or more multiply-accumulate devices each including

-   -   a plurality of multiplication units that generates, on the basis        of the electrical signal input into each of the plurality of        input lines, a charge corresponding to a product value obtained        by multiplying the input value by a weight value,    -   an accumulation unit that accumulates the charge corresponding        to the product value generated by each of the plurality of        multiplication units,    -   a charging unit that charges, after the input period, the        accumulation unit in which the charge corresponding to the        product value is accumulated, and    -   an output unit that outputs, after charging by the charging unit        starts, a multiply-accumulate signal representing a sum of the        product values by performing threshold determination on a        voltage retained by the accumulation unit by using a        predetermined threshold value, in which

in the one or more multiply-accumulate devices, the charging by thecharging unit is performed on a common charging mode and a commonthreshold value is set as the predetermined threshold value.

-   (2) The arithmetic apparatus according to (1), in which

the one or more multiply-accumulate devices are a plurality ofmultiply-accumulate devices connected in parallel to the plurality ofinput lines.

-   (3) The arithmetic apparatus according to (1) or (2), in which

the common charging mode includes charging in which a same charge signalis supplied during a common charging period.

-   (4) The arithmetic apparatus according to any one of (1) to (3), in    which

the common charging mode includes charging at a common charging speed.

-   (5) The arithmetic apparatus according to any one of (1) to (4), in    which

the common charging mode includes charging according to a common timeconstant.

-   (6) The arithmetic apparatus according to any one of (1) to (5), in    which

defining a sum total of absolute values of the weight values set in theplurality of multiplication units as a weight sum total value, thecommon charging mode includes charging based on a maximum value of theweight sum total value among the one or more multiply-accumulatedevices.

-   (7) The arithmetic apparatus according to (5) or (6), in which

each of the one or more multiply-accumulate devices includes a chargeoutput line,

the plurality of multiplication units outputs the charge correspondingto the product value to the charge output line, and

the common charging mode includes charging in which a time constantassociated with the output of the charge corresponding to the productvalue to the charge output line by the plurality of multiplication unitsthe weight sum total value of which is the maximum value is used as thecommon time constant.

-   (8) The arithmetic apparatus according to any one of (1) to (7), in    which

the common threshold value is set on the basis of a duration of theinput period.

-   (9) The arithmetic apparatus according to any one of (1) to (8), in    which

defining a sum total of absolute values of the weight values set in theplurality of multiplication units as a weight sum total value, thecommon threshold value is set on the basis of a maximum value of theweight sum total value among the one or more multiply-accumulatedevices.

-   (10) The arithmetic apparatus according to any one of (1) to (9), in    which

the common charging mode includes charging in which a same charge signalis supplied during the common charging period, and

the charging unit includes a charging line that is connected to theaccumulation unit and supplies the same charge signal to theaccumulation unit during the common charging period.

-   (11) The arithmetic apparatus according to any one of (1) to (9), in    which

the common charging mode includes charging in which a same charge signalis supplied during the common charging period, and

the charging unit supplies the same charge signal to the accumulationunit via the plurality of input lines during the common charging period.

-   (12) The arithmetic apparatus according to any one of (1) to (11),    in which

the plurality of multiplication units includes at least one of apositive weight multiplication unit that generates a positive weightcharge corresponding to a product value obtained by multiplying theinput value by a positive weight value or a negative weightmultiplication unit that generates a negative weight chargecorresponding to a product value obtained by multiplying the input valueby a negative weight value,

the accumulation unit includes a positive charge accumulation unitcapable of accumulating the positive weight charge generated by thepositive weight multiplication unit and a negative charge accumulationunit capable of accumulating the negative weight charge generated by thenegative weight multiplication unit,

the charging unit charges the positive charge accumulation unit and thenegative charge accumulation unit on the common charging mode, and

the output unit outputs the multiply-accumulate signal by performingthreshold determination on each of the positive charge accumulation unitand the negative charge accumulation unit by using the common thresholdvalue.

-   (13) The arithmetic apparatus according to (12), in which

defining a sum total of the positive weight values set in the pluralityof multiplication units as a positive sum total value and a sum total ofthe absolute values of the negative weight values as a negative sumtotal value, the common charging mode includes charging based on amaximum value among the positive sum total values and the negative sumtotal values in the one or more multiply-accumulate devices.

-   (14) The arithmetic apparatus according to (13), in which

each of the one or more multiply-accumulate devices includes a positivecharge output line and a negative charge output line,

the positive charge multiplication unit outputs the positive weightcharge to the positive charge output line,

the negative charge multiplication unit outputs the negative weightcharge to the negative charge output line, and

assuming that the maximum value among the positive sum total values andthe negative sum total values in the one or more multiply-accumulatedevices is a maximum sum total value,

-   -   that the positive weight charge or the negative weight charge        related to the maximum sum total value is a maximum weight        charge, and    -   that the positive charge output line or the negative charge        output line from which the maximum weight charge is output is a        maximum charge output line,

defining a time constant associated with the output of the maximumweight charge to the maximum charge output line as a common timeconstant, the common charging mode includes charging according to thecommon time constant.

-   (15) The arithmetic apparatus according to any one of (12) to (14),    in which

defining a sum total of the positive weight values set in the pluralityof multiplication units as a positive sum total value and a sum total ofthe absolute values of the negative weight values as a negative sumtotal value, the common threshold value is set on the basis of a maximumvalue among the positive sum total values and the negative sum totalvalues in the one or more multiply-accumulate devices.

-   (16) The arithmetic apparatus according to any one of (12) to (15),    in which

the positive weight value and the absolute value of the negative weightvalue are fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set, and

in the one or more multiply-accumulate devices, a value obtained byadding the positive sum total value and the negative sum total value isa common value.

-   (17) The arithmetic apparatus according to any one of (12) to (15),    in which

the positive weight value and the absolute value of the negative weightvalue are fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set, and

in the one or more multiply-accumulate devices, a value obtained byadding the positive sum total value and the negative sum total value isa random value.

-   (18) The arithmetic apparatus according to any one of (12) to (17),    in which

the common charging mode includes charging in which a same charge signalis supplied during the common charging period, and

the charging unit includes a charging line that is connected to thepositive charge accumulation unit and the negative charge accumulationunit and supplies the same charge signal to the positive chargeaccumulation unit and the negative charge accumulation unit during thecommon charging period.

-   (19) The arithmetic apparatus according to any one of (12) to (18),    in which

the common charging mode includes charging in which a same charge signalis supplied during the common charging period, and

the charging unit supplies the same charge signal to the positive chargeaccumulation unit and the negative charge accumulation unit via theplurality of input lines during the common charging period.

-   (20) A multiply-accumulate system, including:

a plurality of input lines into each of which an electrical signalcorresponding to an input value is input within a predetermined inputperiod;

one or more multiply-accumulate devices each including

-   -   a plurality of multiplication units that generates, on the basis        of the electrical signal input into each of the plurality of        input lines, a charge corresponding to a product value obtained        by multiplying the input value by a weight value,    -   an accumulation unit that accumulates the charge corresponding        to the product value generated by each of the plurality of        multiplication units,    -   a charging unit that charges, after the input period, the        accumulation unit in which the charge corresponding to the        product value is accumulated, and    -   an output unit that outputs, after charging by the charging unit        starts, a multiply-accumulate signal representing a sum of the        product values by performing threshold determination on a        voltage retained by the accumulation unit by using a        predetermined threshold value; and

a network circuit configured by connecting the plurality of analogcircuits, in which

in the one or more analog circuits, the charging by the charging unit isperformed on a common charging mode and a common threshold value is setas the predetermined threshold value.

-   (21) The arithmetic apparatus according to any one of (1) to (19),    in which

the electrical signal corresponding to the input value is a pulse signalwhose ON time duration with respect to the input period corresponds tothe input value.

-   (22) The arithmetic apparatus according to any one of (1) to (19)    and (21), in which

the common charging period has a duration equal to the input period.

REFERENCE SIGNS LIST

-   T input period-   θ threshold value-   1 signal line-   3 analog circuit-   6 input signal line-   7 pair of output lines-   7 a positive charge output line-   7 b negative charge output line-   8 synapse circuit (multiplication unit)-   8 a synapse circuit (positive weight multiplication unit)-   8 b synapse circuit (negative weight multiplication unit)-   9 neuron circuit-   10 output signal line-   11 accumulation unit-   12 signal output unit-   13 capacitor-   15 charging unit-   17 resistor-   17 a positive resistor-   17 b negative resistor-   19 charging line-   20, 20 a, 20 b resistor in charging unit-   22, 22 a, 22 b comparator-   23 signal generation unit-   25, 25 a, 25 b current source-   26 differential amplification circuit-   100 arithmetic apparatus

1. An arithmetic apparatus, comprising: a plurality of input lines intoeach of which an electrical signal corresponding to an input value isinput within a predetermined input period; and one or moremultiply-accumulate devices each including a plurality of multiplicationunits that generates, on a basis of the electrical signal input intoeach of the plurality of input lines, a charge corresponding to aproduct value obtained by multiplying the input value by a weight value,an accumulation unit that accumulates the charge corresponding to theproduct value generated by each of the plurality of multiplicationunits, a charging unit that charges, after the input period, theaccumulation unit in which the charge corresponding to the product valueis accumulated, and an output unit that outputs, after charging by thecharging unit starts, a multiply-accumulate signal representing a sum ofthe product values by performing threshold determination on a voltageretained by the accumulation unit by using a predetermined thresholdvalue, wherein in the one or more multiply-accumulate devices, thecharging by the charging unit is performed on a common charging mode anda common threshold value is set as the predetermined threshold value. 2.The arithmetic apparatus according to claim 1, wherein the one or moremultiply-accumulate devices are a plurality of multiply-accumulatedevices connected in parallel to the plurality of input lines.
 3. Thearithmetic apparatus according to claim 1, wherein the common chargingmode includes charging in which a same charge signal is supplied duringa common charging period.
 4. The arithmetic apparatus according to claim1, wherein the common charging mode includes charging at a commoncharging speed.
 5. The arithmetic apparatus according to claim 1,wherein the common charging mode includes charging according to a commontime constant.
 6. The arithmetic apparatus according to claim 1, whereindefining a sum total of absolute values of the weight values set in theplurality of multiplication units as a weight sum total value, thecommon charging mode includes charging based on a maximum value of theweight sum total value among the one or more multiply-accumulatedevices.
 7. The arithmetic apparatus according to claim 5, wherein eachof the one or more multiply-accumulate devices includes a charge outputline, the plurality of multiplication units outputs the chargecorresponding to the product value to the charge output line, and thecommon charging mode includes charging in which a time constantassociated with the output of the charge corresponding to the productvalue to the charge output line by the plurality of multiplication unitsthe weight sum total value of which is the maximum value is used as thecommon time constant.
 8. The arithmetic apparatus according to claim 1,wherein the common threshold value is set on a basis of a duration ofthe input period.
 9. The arithmetic apparatus according to claim 1,wherein defining a sum total of absolute values of the weight values setin the plurality of multiplication units as a weight sum total value,the common threshold value is set on a basis of a maximum value of theweight sum total value among the one or more multiply-accumulatedevices.
 10. The arithmetic apparatus according to claim 1, wherein thecommon charging mode includes charging in which a same charge signal issupplied during the common charging period, and the charging unitincludes a charging line that is connected to the accumulation unit andsupplies the same charge signal to the accumulation unit during thecommon charging period.
 11. The arithmetic apparatus according to claim1, wherein the common charging mode includes charging in which a samecharge signal is supplied during the common charging period, and thecharging unit supplies the same charge signal to the accumulation unitvia the plurality of input lines during the common charging period. 12.The arithmetic apparatus according to claim 1, wherein the plurality ofmultiplication units includes at least one of a positive weightmultiplication unit that generates a positive weight chargecorresponding to a product value obtained by multiplying the input valueby a positive weight value or a negative weight multiplication unit thatgenerates a negative weight charge corresponding to a product valueobtained by multiplying the input value by a negative weight value, theaccumulation unit includes a positive charge accumulation unit capableof accumulating the positive weight charge generated by the positiveweight multiplication unit and a negative charge accumulation unitcapable of accumulating the negative weight charge generated by thenegative weight multiplication unit, the charging unit charges thepositive charge accumulation unit and the negative charge accumulationunit on the common charging mode, and the output unit outputs themultiply-accumulate signal by performing threshold determination on eachof the positive charge accumulation unit and the negative chargeaccumulation unit by using the common threshold value.
 13. Thearithmetic apparatus according to claim 12, wherein defining a sum totalof the positive weight values set in the plurality of multiplicationunits as a positive sum total value and a sum total of the absolutevalues of the negative weight values as a negative sum total value, thecommon charging mode includes charging based on a maximum value amongthe positive sum total values and the negative sum total values in theone or more multiply-accumulate devices.
 14. The arithmetic apparatusaccording to claim 13, wherein each of the one or moremultiply-accumulate devices includes a positive charge output line and anegative charge output line, the positive charge multiplication unitoutputs the positive weight charge to the positive charge output line,the negative charge multiplication unit outputs the negative weightcharge to the negative charge output line, and assuming that the maximumvalue among the positive sum total values and the negative sum totalvalues in the one or more multiply-accumulate devices is a maximum sumtotal value, that the positive weight charge or the negative weightcharge related to the maximum sum total value is a maximum weightcharge, and that the positive charge output line or the negative chargeoutput line from which the maximum weight charge is output is a maximumcharge output line, defining a time constant associated with the outputof the maximum weight charge to the maximum charge output line as acommon time constant, the common charging mode includes chargingaccording to the common time constant.
 15. The arithmetic apparatusaccording to claim 12, wherein defining a sum total of the positiveweight values set in the plurality of multiplication units as a positivesum total value and a sum total of the absolute values of the negativeweight values as a negative sum total value, the common threshold valueis set on a basis of a maximum value among the positive sum total valuesand the negative sum total values in the one or more multiply-accumulatedevices.
 16. The arithmetic apparatus according to claim 12, wherein thepositive weight value and the absolute value of the negative weightvalue are fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set, and in the one ormore multiply-accumulate devices, a value obtained by adding thepositive sum total value and the negative sum total value is a commonvalue.
 17. The arithmetic apparatus according to claim 12, wherein thepositive weight value and the absolute value of the negative weightvalue are fixed to a same value, set to any one of the plurality ofvalues different from each other, or randomly set, and in the one ormore multiply-accumulate devices, a value obtained by adding thepositive sum total value and the negative sum total value is a randomvalue.
 18. The arithmetic apparatus according to claim 12, wherein thecommon charging mode includes charging in which a same charge signal issupplied during the common charging period, and the charging unitincludes a charging line that is connected to the positive chargeaccumulation unit and the negative charge accumulation unit and suppliesthe same charge signal to the positive charge accumulation unit and thenegative charge accumulation unit during the common charging period. 19.The arithmetic apparatus according to claim 12, wherein the commoncharging mode includes charging in which a same charge signal issupplied during the common charging period, and the charging unitsupplies the same charge signal to the positive charge accumulation unitand the negative charge accumulation unit via the plurality of inputlines during the common charging period.
 20. A multiply-accumulatesystem, comprising: a plurality of input lines into each of which anelectrical signal corresponding to an input value is input within apredetermined input period; one or more multiply-accumulate devices eachincluding a plurality of multiplication units that generates, on a basisof the electrical signal input into each of the plurality of inputlines, a charge corresponding to a product value obtained by multiplyingthe input value by a weight value, an accumulation unit that accumulatesthe charge corresponding to the product value generated by each of theplurality of multiplication units, a charging unit that charges, afterthe input period, the accumulation unit in which the chargecorresponding to the product value is accumulated, and an output unitthat outputs, after charging by the charging unit starts, amultiply-accumulate signal representing a sum of the product values byperforming threshold determination on a voltage retained by theaccumulation unit by using a predetermined threshold value; and anetwork circuit configured by connecting the plurality of analogcircuits, wherein in the one or more analog circuits, the charging bythe charging unit is performed on a common charging mode and a commonthreshold value is set as the predetermined threshold value.